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Programming 66
3.7 Example of Network Interrupt Handling
The following is an example of the steps necessary to set up the RFM ‐ 5565 to
generate a PCI interrupt in response to one of the four basic network interrupts.
This example also lists the steps necessary to service that interrupt. When using
this example, it is advisable to examine Figure 2 ‐ 1 on page 26 and Figure 3 ‐ 1 on
page 60 to obtain a visual sense of the circuitry involved.
3.7.1 Setup
1. Clear any prior unscheduled interrupts in the SID1 FIFO by writing zero (0)
to the SID1 at PCIBAR2 + offset $24.
2. Clear any prior unscheduled interrupts in the SID2 FIFO by writing zero (0)
to the SID2 at PCIBAR2 + offset $2C.
3. Clear any prior unscheduled interrupts in the SID3 FIFO by writing zero (0)
to the SID3 at PCIBAR2 + offset $34.
4. Clear any prior unscheduled interrupts in the SID4 FIFO by writing zero (0)
to the SID4 at PCIBAR2 + offset $3C.
5. Using a read ‐ modify ‐ write operation, set Bit 07, Bit 02, Bit 01 and Bit 00 high
(1) in the LIER register at PCIBAR2 + offset $14. This allows any one of the
four basic network interrupts to assert the onboard signal LINTi#, provided
the global enable in the LISR is also high (1).
6. Write the value $4000 to the LISR register at PCIBAR2 + offset $10. The value
$4000 sets the Global Interrupt Enable (Bit 14) high (1) and clears any unre ‐
lated sources. You may prefer to use a read ‐ modify ‐ write operation if other
sources in the LISR are to remain unchanged.
7. Using a read ‐ modify ‐ write operation, set Bit 8 and Bit 11 high (1) in the
INTCSR register at PCIBAR0 + offset $68. Bit 8 is the PCI Interrupt Enable
and Bit 11 is the Local Interrupt Input (LINTi#) Enable.
3.7.2 Servicing Network Interrupts
Read the INTCSR register at PCIBAR0 + offset $68. Verify that the Local Interrupt
Input Active (Bit 15) is high (1). If Bit 15 is not high, or if another interrupt source
within the INTCSR has priority, then the user’s interrupt service routine would
take different steps from this point on.
Read the LISR register at PCIBAR2 + offset $10. Determine if the Pending
Network Interrupt 4 (Bit 07), the Pending Network Interrupt 3 (Bit 02), the
Pending Network Interrupt 2 (Bit 01), or the Pending Network Interrupt 1
(Bit 00) is high (1).
Assuming, for example, the previous step indicates Network Interrupt 2 is
pending, read the Interrupt 2 Sender Data FIFO at PCIBAR2 + offset $28 and place
the value in the desired user location. If the user is not passing data with the
interrupt, then this step is unnecessary and may be skipped.
Read the Interrupt 2 Sender ID FIFO at PCIBAR2 + offset $2C and place the value
in the desired user location. This value is the node ID of the source of the network
interrupt. Provided that there are no additional network interrupts stored in the
Sender ID FIFO, the act of reading this value will de ‐ assert the Pending Network
Interrupt 2 bit (Bit 01) in the LISR, which in turn de ‐ asserts the LINTi# line. De ‐
asserting the LINTi# line will de ‐ assert the PCI interrupt.