GE MAC 5000, Руководство по обслуживанию

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Revision B MAC
™
5000 resting ECG analysis system 2-25
2024917-010
Equipment Overview: Theory of Operation
The FPGA PWM output signals contain a substantial amount of noise
from +3V-M supply fluctuations. To reduce noise and establish an
accurate reference level, the PWM signals are buffered by CMOS
inverters (U18) that are powered from REF2V5. Although the CMOS
inverters are powered by 2.5 Volts but are driven by 3.3 Volt logic, no
problem exists as this is allowed with VHC logic. The PWM output
signals are then low pass filtered (R187,C186, etc) before being passed to
the output amplifiers. The ECG output channel amplifier injects an
offset current derived from REF2V5 to achieve bipolar operation. The DC
outputs operate in unipolar fashion, eliminating the vexing MAX-1 offset
problems. No zero calibration is required for the DC outputs. Since the
ECG output is an AC signal, no offset adjust is required there either.
The output amplifiers provide additional low pass filtering (R180,C178,
etc.). ESD protection and additional PWM carrier filtering is provided by
0.1
μ F filter capacitors. To prevent amplifier oscillation, blocking
resistors are placed between the amplifier outputs and the filter
capacitors.
Beep Generator
A simple tone generator with two volume levels provides system beeps
and key clicks. Frequencies of 250Hz, 500Hz and 1KHz are provided at
both low and high volume. The logic level output signal drives LS1
through an open collector transistor driver Q100. Full volume is achieved
by driving the fundamental beep tone directly to the speaker. Half
volume is achieved by gating the speaker signal with a 24MHz square
wave, reducing the amplitude by 50%. The LS1 is also used by the
communication board for modem sound. The modem speaker signal from
the module is amplified and driven though Q101.
PC Card Logic.
The -006 board is designed to support multiple product and one of the
requirement during the design phase was the support for PC Card,
through a daughter board. But this requirement was removed later on.
The PC Card logic use the two ATMEL chip select signals and bus
control signals to generate, IO, Memory and Attribute memory access to
PC Card. The PC Card bus controls signals from FPGA and the address
and data lines form ATMEL are buffered and terminated to daughter
board interface connector J21.
SDRAM
Program code and working data is stored in a four 4MWord bank of
32-bit wide memory (64Mbytes). This memory is made up of two 256
Mbit SDRAMs each 16 bits wide. All bus timing and refresh control is
performed by the ATMEL CPU SDRAM controller. The SDRAM clock
rate is one third of the ATMEL CPU clock or 59.904 Mhz. Though the
size requirement is less, the video frame buffer also use 256Mbit
SDRAM.