GE MAC 5000, Руководство по обслуживанию

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Revision B MAC
™
5000 resting ECG analysis system 2-11
2024917-010
Equipment Overview: Theory of Operation
VAna+, VAna-
The analog output circuitry is powered by a low current switched 12V
rail, provided by the Main Regulator. VAna+ provides the positive supply
for the output op-amps. A charge pump voltage inverter is provided to
produce an approximate -11V rail for the op-amps. Although only the
ECG output is bipolar, all output amplifiers are driven from VAna-.
A short circuit on either of the unipolar DC outputs could load VAna-
sufficiently to affect the negative peak swing of the ECG output. The
ECG and DC outputs are not required to operate correctly in the
presence of abnormal loads.
Clocks
Super I/O and FPGA
Both of these devices uses the 24 Mhz clock oscillator Y5 to drive their
internal requirements for various clock frequencies. The main function of
the Super I/O IC is the floppy drive interface and all the needed timing
comes from this oscillator. The FPGA provides many functions including
the acquisition interface, the printer interface, and the Stooges interface
(Bbus) to name a few. The FPGA uses a built-in frequency doubler to
raise this 24 Mhz clock to 48 Mhz for internal use. All functions inside
the FPGA use the clocks derived from 48MHz. The main derived clocks
are:
‹
1 MHz for acquisition interface
‹
4 MHz for printer data shift clock interface.
‹
4 MHz for EEPROM data shift clock
‹
24MHz for VGA LCD panel clock.
The VGA LCD controller, that include the SDRAM frame buffer
controller use 59.904 MHz external memory clock from ATMEL CPU in
addition to the 48MHz FPGA clock
CPU ATMEL AT91RM9200
The ATMEL AT91RM9200 has two oscillators. Slow Clock oscillator and
Main Oscillator. The Slow Clock Oscillator use 32,768 KHz crystal for
clock generation. The CPU runs in Slow Clock mode (@48MHz) after
system reset. Slow clock is also used by the built in RTC. But the -006
board do not use the ATMEL RTC for the system timing requirements.
The Main oscillator use 18.432 MHz crystal. Processor clock (179.712
MHz), Master clock (59.904) for external Bus Interface and Peripheral
Clocks are derived from main oscillator by the Master Clock Controller.