342-86400-498PS
Issue 1.2
April 2012
Page 73
Copyright
GE Multilin Inc. 2010-2012
-
The order of the STS-1 SPEs received in this TDM pipe has
been changed with respect to their order at the far end.
Framing
– Loss of frame synchronization;
RDI
– Abnormal condition of at least one of the transmitted STS-1
SPEs (as received at the far-end unit);
L/R Mismatch
– Inter-ETHER-1000/ETHER-100 connection is not
Left to Right;
OK
– The status of the Line port is OK (as far as this TDM pipe is
concerned).
Note
: The field is disabled if no SPE slots have been assigned to this
TDM pipe or the respective Topology field is set to Off or Linear-R/L
36
.
BER
Displays the current bit error rate detected on each Line Port (per TDM
pipe).
Note
: The field is disabled if no SPE slots have been assigned to this
TDM pipe or the respective Topology field is set to Off or Linear-R/L
37
.
CV
Displays the current cumulative count of bit errors detected on each
Line Port (per TDM pipe). The "Clear CV Counts" button (either the
one in the Main Tab or the one in the Line Monitor Tab) resets the CV
counters.
Note
: The field is disabled if no SPE slots have been assigned to this
TDM pipe or the respective Topology field is set to Off or Linear-R/L
38
.
Usage-IN/OUT (Now and Peak)
Displays the current (Now) and Peak bandwidth usage in the left and
right Line ports‟ TDM pipes and on the FPGA's Drop port, for both IN
and OUT directions.
39
The peak usage refers to the maximum
bandwidth usage over the most recent period of time whose duration is
35
If the far-end unit connected to this TDM pipe is ETHER-100, its Qty Slots field setting is not
matching the total number of slots assigned to this TDM pipe locally.
36
Linear-R for the Left Line port. Linear-L for the Right Line port.
37
Linear-R for the Left Line port. Linear-L for the Right Line port.
38
Linear-R for the Left Line port. Linear-L for the Right Line port.
39
The FPGA's Drop port is an internal port between FPGA and CPU. The FPGA's Drop-OUT
traffic refers to the total traffic dropped locally before D-PVLAN (and QVLAN) egress filtering has
been applied. The FPGA's Drop-IN refers to the total traffic added locally after QVLAN ingress
filtering (if any) has been applied. Note that the D-PVLAN and QVLAN filtering does not affect
the DA-known unicast traffic.