GE Digital Energy L60, Инструкция по эксплуатации

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CHAPTER 9: THEORY OF OPERATION OVERVIEW
L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL 9-7
9
In this final figure AND1 (the comparer) at each end of the line compares the coincidence time of the positive half-cycle of
current with the absence of receiver output. This is initiated only when a fault is present as indicated by an output from
FDH (Fault Detector High-set). FDH is set so that it does not pick up on load current but does pick up for all faults on the
protected line section. Thus, when a fault occurs, FDH picks up, and if the receiver output is not present for 3 ms during the
positive half cycle of current out of the mixing network, a trip output is obtained.
Of course, the output from the receiver depends on the keying of the remote transmitter. The transmitters at all line
terminals are keyed in the same manner. They are keyed ON by an output from FDL (Fault Detector Low-set) and keyed OFF
by the squaring amplifier via AND2 during the positive half cycles of current. The FDL function is required at all terminals in
all phase comparison blocking schemes to initiate a blocking signal from the associated transmitter. This is received at the
remote receiver and blocks tripping via the comparer during external faults. FDL has a more sensitive setting and therefore
operates faster than the remote FDH function. It is obvious from the Three-Terminal Line Phase Comparison figure that if
an external fault occurred, and FDL did not operate at least as fast as the remote FDH, false tripping can occur because of
the lack of receiver output. In general, FDL is set so as not to pick up on load current but still with a lower pick up than FDH
so that it operates before FDH. For an internal fault, the currents entering both ends of the line are in phase with each
other. Thus, during the half-cycle that the SQ AMP is providing an input to AND1, the associated receiver is producing no
output, and so tripping takes place at both ends of the line.
For an external fault, the current entering one terminal is 180° out of phase with the current entering the other terminal.
Under these conditions, during the half-cycles when the SQ AMP is producing outputs, the associated receiver is also
providing an output thus preventing an AND1 output. No tripping takes place.
9.1.3 Variations in phase comparison schemes
There are several phase comparison schemes in general use today and while all of these employ the same basic means of
comparison described earlier, significant differences exist. These differences relate to the following:
•
Phase comparison excitation (component or current to be compared)
• Pure phase comparison versus combined phase and directional comparison
• Blocking versus tripping schemes
• Single versus dual phase comparison
9.1.4 Phase comparison excitation
9.1.4.1 Description
Before discussing this subject, it is well to consider what takes place in terms of the currents that are available for
comparison when a fault occurs on a power system. The table lists the sequence components of fault current that are
present during the various different kinds of faults while the following figure illustrates the relative phase positions of the
sequence components of fault current for the different kinds of faults and the different phases involved.
Table 9-1: Fault types
Type of fault Sequence components
Positive
Negative Zero
Single-Phase-to-Ground yes yes yes
Phase-to-Phase yes yes no
Double-Phase-to-Ground yes yes yes
Three-Phase yes no no