GE Digital Energy L60, Инструкция по эксплуатации

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5-242 L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL
GROUPED ELEMENTS CHAPTER 5: SETTINGS
5
When the scheme is initiated, it immediately sends a trip signal to the breaker initially signaled to trip (this feature is usually
described as re-trip). This reduces the possibility of widespread tripping that results from a declaration of a failed breaker.
Determination of a breaker failure condition
The schemes determine a breaker failure condition via three paths. Each of these paths is equipped with a time delay, after
which a failed breaker is declared and trip signals are sent to all breakers required to clear the zone. The delayed paths are
associated with breaker failure timers 1, 2, and 3, which are intended to have delays increasing with increasing timer
numbers. These delayed paths are individually enabled to allow for maximum flexibility.
Timer 1 logic (early path) is supervised by a fast-operating breaker auxiliary contact. If the breaker is still closed (as
indicated by the auxiliary contact) and fault current is detected after the delay interval, an output is issued. Operation of
the breaker auxiliary switch indicates that the breaker has mechanically operated. The continued presence of current
indicates that the breaker has failed to interrupt the circuit.
Timer 2 logic (main path) is not supervised by a breaker auxiliary contact. If fault current is detected after the delay interval,
an output is issued. This path is intended to detect a breaker that opens mechanically but fails to interrupt fault current; the
logic therefore does not use a breaker auxiliary contact.
The timer 1 and 2 paths provide two levels of current supervision, high-set and low-set, that allow the supervision level to
change from a current which flows before a breaker inserts an opening resistor into the faulted circuit to a lower level after
resistor insertion. The high-set detector is enabled after timeout of timer 1 or 2, along with a timer that enables the low-set
detector after its delay interval. The delay interval between high-set and low-set is the expected breaker opening time.
Both current detectors provide a fast operating time for currents at small multiples of the pickup value. The overcurrent
detectors are required to operate after the breaker failure delay interval to eliminate the need for very fast resetting
overcurrent detectors.
Timer 3 logic (slow path) is supervised by a breaker auxiliary contact and a control switch contact used to indicate that the
breaker is in or out-of-service, disabling this path when the breaker is out-of-service for maintenance. There is no current
level check in this logic as it is intended to detect low magnitude faults and it is therefore the slowest to operate.
Output
The outputs from the schemes are:
•
FlexLogic operands that report on the operation of portions of the scheme
• FlexLogic operand used to re-trip the protected breaker
• FlexLogic operands that initiate tripping required to clear the faulted zone. The trip output can be sealed-in for an
adjustable period.
• Target message indicating a failed breaker has been declared
• Illumination of the faceplate Trip LED (and the Phase A, B, or C LED, if applicable)
Main path sequence
Figure 5-131: Breaker failure main path sequence
The current supervision elements reset in less than 0.7 of a power cycle for any multiple of pickup current as shown in the
following figure.
PROTECTION OPERATION BREAKER INTERRUPTING TIME
CALCULATED CURRENT MAGNITUDE
ACTUAL CURRENT MAGNITUDE
FAILED INTERRUPTION
CORRECT INTERRUPTION
Rampdown
(ASSUMED 1.5 cycles)
INITIATE (1/8 cycle)
BREAKER FAILURE TIMER No. 2 (±1/8 cycle)
BREAKER FAILURE CURRENT DETECTOR PICKUP (1/8 cycle)
BREAKER FAILURE OUTPUT RELAY PICKUP (1/4 cycle)
FAULT
OCCURS
1 2 3 4 5 6 7 8 9 10 11 0
0
0
AMP
(ASSUMED 3 cycles)
cycles
827083A6.CDR
MARGIN
(Assumed 2 Cycles)
BACKUP BREAKER OPERATING TIME
(Assumed 3 Cycles)