FUSHENGTEK Technology WG-7302-E38/J19, Руководство пользователя

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WG-7302 User’s Guide
7.4 LVDS Flat Panel Connector (J8)
The LVDS and eDP connector is based on 40 pole connector.
The Connector reserved to automatically adjust the screen brightness ALS (Ambient Lightsensor) InterfaceforeDP
(Supported on win8 or win 8.1system).
Note Type Signal PIN Signal Type Note
Default 5V PWR +5V or +12V 1 2 LVDS B3+ LVDS
PWR LCD_VCC 3 4 LVDS B3- LVDS
OT BKLTEN# 5 6 LVDS B2+ LVDS
OT BKLTCTL 7 8 LVDS B2- LVDS
OT DDC CLK 9 10 LVDS B1+ LVDS
OT DDC DATA 11 12 LVDS B1- LVDS
Aux(-) channel used by eDP
Aux Ch(n) 13 14 LVDS B0+ LVDS
Aux(+) channel used by eDP
Aux Ch(p) 15 16 LVDS B0- LVDS
I INT# 17 18 LVDS BCLK+ LVDS
LVDS LVDS A3+ 19 20 LVDS BCLK- LVDS
LVDS LVDS A3- 21 22 GND PWR
LVDS LVDS A2+ 23 24 Lane 3(p) LVDS
LVDS LVDS A2- 25 26 Lane 3(n) LVDS
LVDS LVDS A1+ 27 28 Lane 2(p) LVDS
LVDS LVDS A1- 29 30 Lane 2(n) LVDS
LVDS LVDS A0+ 31 32 Lane 1(p) LVDS used by eDP
LVDS LVDS A0- 33 34 Lane 1(n) LVDS used by eDP
LVDS
LVDS ACLK+
35 36 Lane 0(p) LVDS used by eDP
LVDS LVDS ACLK- 37 38 Lane 0(n) LVDS used by eDP
PWR GND 39 40 Hot Plug I Internally pull down
(100K ohm)
Note : The LVDS connector supports single and dual channel, 18/24bit SPWG panels up to a resolution of 1920x1080
and with limited frame rate up to 1920x1200.
Signal Description
LVDS A0..A3 LVDS A Channel data
LVDS ACLK LVDS A Channel clock
LVDS B0..B3 LVDS B Channel data
LVDS BCLK LVDS B Channel clock
BKLTCTL Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN# Backlight Enable signal (active low) (2)
LCDVCC
VCC supply to the display. 5V or 3.3V (1A Max.) selected in BIOS setup menu. Power sequencing
depends on LVDS panel selection. (Shared with eDP connector)
DDC CLK DDC Channel ClockorAmbient Light SensorI2C clock
DDC DATA DDC Channel Data or Ambient Light SensorI2Cdata
INT# Ambient Light SensorInterrupt