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mirror function is analogic to CPU one and is similary
default on after reset. When small model is selected,
then FPGA decoding logic works as described on The
Mainboard User Reference chapter for SMALL.
RESET:
when a ‘0’ to ‘1’ occurs on this bit, the CPU will be
reset (a 100ms pulse will be generated on the #RST
CPU pin). This bit is always ‘0’ when being read.
Initial Values description:
•
after power-on or system reset, the bits 0 - 5 holds values from User
Switches Status register
•
after software reset CPU is set to mode defined by actual values of
MD0-MD2
•
if MD0-MD2 are set to values defined for CPU Serial programming
mode, FPGA sets the logic levels on the CPU port P0 in the way that
P00 and P01 pins of the CPU are pulled to ‘0’. This invokes the
asynchronous serial programming mode of the CPU.
Note: if the FPGA detects that some of the CPU signals MD0-2, P00,P01
are set to ”0” by CPU board switches during reset time, it holds RST to
”0” and periodically flashes the green LED “FPGA st.” (D9) on the Main
board. Please switch all CPU board switches on SW3 to OFF when Main
board is used.
