68
68
68
68
(1) Bus status register
IBSR
7
6
5
4
3
2
1
0
Address: C9
H
BB
---
---
LRB
TRX
---
---
---
Read/Write
(R)
(---)
(---)
(R)
(R)
(---)
(---)
(---)
Initial Value
(0)
(---)
(---)
(0)
(1)
(---)
(---)
(---)
[Bit 7]
BB
: Bus Busy
0: The Stop condition was transmitted (initial value)
1: The Start condition was transmitted
This bit should be polled when the MS bit of the IBCR register is changed
by user.
[Bit 4]
LRB
: Last Received Bit
This bit stores the acknowledge bit (the acknowledge bit is the 9
th
bit of the
data byte).
[Bit 3]
TRX:
Transmit/Receive
This bit indicates data transmitting and receiving.
0
: Receive mode - the current (or the next) transfer will be reception of a
byte from a slave.
1
: Transmit mode [initial value] - the current transfer will be transmission to
the slave.
This bit is set when the first byte after a START condition is written to the
IDAR register. It contains the state of the LSB bit of the first byte.
(2) Bus control register
IBCR
7
6
5
4
3
2
1
0
Address: CA
H
---
---
SCC
MTS
ACK
--
INTE
INT
Read/Write
(---)
(---)
(R/W)
(R/W)
(R/W)
(---)
(R/W)
(R/W)
Initial Value
(---)
(---)
(0)
(0)
(0)
(---)
(0)
(0)
[Bit 5]
SCC:
Start Condition Continue
This bit generates the start condition.
•
Write
0
: Not applicable [Initial value]
1
: The start condition is generated and address data transfer is started.
•
Read
An '1' will be read out of this bit if it was previously written to it, until
the start condition is generated. After finishing the Start condition
transmission, this bit is reset to '0'.
