Freescale Semiconductor PXR4030, Справочное руководство

Страница: 897 / 1434

Deserial Serial Peripheral Interface (DSPI)
Freescale Semiconductor 25-37
PXR40 Microcontroller Reference Manual, Rev. 1
TXNXTPTR equal to two means that the DSPI_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
25.4.3.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by writing to the
DSPI_PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the DSPI_SR is set. The
TFFF bit is cleared when TX FIFO is full and the DMA controller indicates that a write to DSPI_PUSHR
is complete or by host software writing a ‘1’ to the TFFF in the DSPI_SR. The TFFF can generate a DMA
request or an interrupt request. See
Section 25.4.10.2, Transmit FIFO Fill Interrupt or DMA Request , for
details.
The DSPI ignores attempts to push data to a full TX FIFO, i.e. the state of the TX FIFO is unchanged. No
error condition is indicated.
25.4.3.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO Counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPI_SR is set to indicate the
completion of a transfer. The TX FIFO is flushed by writing a ‘1’ to the CLR_TXF bit in DSPI_MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty,
the Transmit FIFO Underflow Flag (TFUF) in the slave’s DSPI_SR is set. See
Section 25.4.10.4, Transmit
FIFO Underflow Interrupt Request , for details.
25.4.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data are removed (popped) from the RX FIFO by
reading the DSPI POP RX FIFO Register (DSPI_POPR). RX FIFO entries can only be removed from the
RX FIFO by reading the DSPI_POPR or by flushing the RX FIFO.
The RX FIFO Counter field (RXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
The POPNXTPTR field in the DSPI_SR points to the RX FIFO entry that is returned when the
DSPI_POPR is read. The POPNXTPTR contains the positive offset from DSPI_RXFR0 in number of
32-bit registers. For example, POPNXTPTR equal to two means that the DSPI_RXFR2 contains the
received SPI data that will be returned when DSPI_POPR is read. The POPNXTPTR field is incremented
every time the DSPI_POPR is read.