Reset Configuration
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
5-11
5.2.7.2 Loading Multiple Devices From a Single I
2
C EEPROM
When the MSC8144E device shares the I
2
C EEPROM device with other MSC8144E devices to
load the reset configuration words, one device must be a reset initiator and the rest must be reset
targets. The definition of reset target or reset initiator is latched internally during power-on reset
sequence. The reset configuration implementation involves a software and glue logic. The
hardware connection is shown in Figure 5-4. The
STOP_BS
signal input to the reset initiator must
be driven low during the power on reset sequence while all the targets inputs must be driven high.
During the power on reset assertion, the initiator cannot drive the
STOP_BS
output bus because its
role as initiator is not enabled. Pull-ups are required;
refer to the MSC8144E Technical Data
sheet for appropriate resistor values to pull the target
STOP_BS
signal inputs high.
In the first stage of reset configuration, the reset initiator reads its own reset configuration words.
It accesses the I
2
C EEPROM while all other reset targets are stopped. When
PORESET
is
deasserted, the
STOP_BS
is latched in the reset block after few cycles and defines the reset
initiator and targets. It also keeps all the reset target I
2
C controllers in idle state while the reset
initiator starts to access the EEPROM target using address 0b1010000. Then the reset initiator
must exit from reset and run the internal code.
In the second stage, the reset initiator reads the target RCWs and stores the values in its memory.
See Chapter 6, Boot Program for how to determine the number of reset targets to be configured.
The reset initiator core reads the target RCWs from the I
2
C EEPROM. Then, it configures its I
2
C
controller to emulate an EEPROM device for each reset target. The reset initiator emulates
EEPROM using the target address 0b1010111.
In the last stage, the reset initiator releases the
STOP_BS
for each target in a known order. The
released reset target accesses the I
2
C bus to read from target address 0b1010111. The order of
reading the target RCWs is the order for their connection.
Содержание MSC8144E
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