Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-65
17.5 Initialization / Application Information
Upon reset all of the unified channels of the eMIOS default to general purpose inputs (GPIO input mode).
17.5.1 Considerations on Changing a UC Mode
Before changing an operating mode, the UC must be programmed to GPIO mode, and EMIOS_CADR n
and EMIOS_CBDR n must be updated with the correct values for the next operating mode. Then the
EMIOS_CCR n can be written with the new operating mode. If a UC is changed from one mode to another
without performing this procedure, the first operating cycle of the selected time base is unpredictable.
NOTE
When interrupts are enabled and an interrupt is generated, the FLAG bits
should be cleared before exiting the interrupt service routine.
17.5.2 Generating Correlated Output Signals
Correlated output signals can be generated by all output operating modes. Bits ODIS n can be used to
control the update of these output signals.
In order to guarantee that the internal counters of correlated channels are incremented in the same clock
cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers
are set after enabling the global prescaler, the internal counters may increment in the same ratio, but at a
different clock cycle.
When an output disable condition occurs, the software interrupt routine must service the output channels
before servicing the channels running SAIC. This procedure avoid glitches in the output pins.
17.5.3 Time Base Generation
For all channel operation modes that generate a time base (MC, OPWFM, OPWM, MCB, OPWFMB and
OPWMB), the clock prescaler can use several ratios calculated as:
The prescaled clocks in Figure 17-55 , Figure 17-56 , and Figure 17-57 illustrate this ratio. For example, if
the ratio is 1, the prescaled clock is high and continuously enables the internal counter (EMIOS_CCNTR n )
( Figure 17-55 ); if the ratio is 3, then it pulses every 3 clock cycles ( Figure 17-56 ) and the internal counter
increments every 3 clock cycles; if the ratio is 9, it pulses every 9 clock cycles, etc. This high pulse enables
the EMIOS_CCNTR
n to increment as long as no other conditions disable this counter. The match signal
is generated by pulsing every time the internal counter matches the programmed match value. Note that
for the same programmed match value, the period is shorter when using a prescaler ratio greater than one.
Ratio GPRE 1 +
 
UCPRE 1 +
  
=