Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-8 Freescale Semiconductor
11.1.2 Overview
The frequency modulated phase locked loop (FMPLL) allows the user to generate high speed system
clocks from an 8 MHz to 20 MHz crystal oscillator or external clock generator. Further, the FMPLL
supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio, modulation depth, and modulation rate are all controllable through a bus
interface.
11.1.3 Features
The FMPLL has the following major features:
• Input clock frequency from 8 MHz to 20 MHz
• Current controlled oscillator (ICO) range from 48 MHz to maximum device frequency
• Reference frequency pre-divider (PREDIV) for finer frequency synthesis resolution
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to
re-lock
• Four modes of operation:
— Bypass mode.
— Crystal reference mode (default mode for MPC5554 and 324 and 416 packages of the
MPC5553). Refer to Section 11.1.4.1, “Crystal Reference (Default Mode) .”
— External reference mode. Refer to Section 11.1.4.2, “External Reference Mode .”
— PLL dual-controller (1:1) mode for EXTAL_EXTCLK to CLKOUT skew minimization.
• Programmable frequency modulation
— Modulation enabled/disabled via bus interface
— Triangle wave modulation
— Register programmable modulation depth (+/-1% to +/-2% deviation from center frequency)
— Register programmable modulation frequency dependent on reference frequency; limited to
100 MHz – 250 MHz.
• Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously
monitors lock status to report loss of lock conditions
— User-selectable ability to generate an interrupt request upon loss of lock. (See
Chapter 10,
“Interrupt Controller (INTC) ,” for details.)
— User-selectable ability to generate a system reset upon loss of lock. (See Chapter 4, “Reset ,”
for details.)
• Loss of clock (LOC) detection for reference and feedback clocks
— User-selectable ability to generate an interrupt request upon loss of clock. (See
Chapter 10,
“Interrupt Controller (INTC) ,” for details.)
— User-selectable ability to generate a system reset upon loss of clock (See Chapter 4, “Reset ,”
for details.)
• Self-clocked mode (SCM) operation in event of input clock failure