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Chapter 5 Background Debug Controller (S12ZBDCV2)
MC9S12ZVM Family Reference Manual Rev. 1.3
170
Freescale Semiconductor
commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other
bits of the transmission are redundant.
Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE
for each byte and setting the ILLACC bit.
5.4.5.2
BDC Access Of Device Memory Mapped Resources
The device memory map is accessed using READ_MEM, DUMP_MEM, WRITE_MEM, FILL_MEM
and READ_SAME, which support different access sizes, as explained in the command descriptions.
When an unimplemented command occurs during a DUMP_MEM, FILL_MEM or READ_SAME
sequence, then that sequence is ended.
Illegal read accesses return a value of 0xEE for each byte. After an illegal access FILL_MEM and
READ_SAME commands are not valid, and it is necessary to restart the internal access sequence with
READ_MEM or WRITE_MEM. An illegal access does not break a DUMP_MEM sequence. After read
accesses that cause the RDINV bit to be set, DUMP_MEM and READ_SAME commands are valid, it is
not necessary to restart the access sequence with a READ_MEM.
The hardware forces low-order address bits to zero for longword accesses to ensure these accesses are
realigned to 0-modulo-size alignments.
Word accesses map to 2-bytes from within a 4-byte field as shown in
. Thus if address bits [1:0]
are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data
from within the addressed 4-byte field.
Table 5-9. CPU Register Number (CRN) Mapping
CPU Register
Valid Data Bits
Command
Opcode
Command
Opcode
D0
[7:0]
WRITE_D0
0x40
READ_D0
0x60
D1
[7:0]
WRITE_D1
0x41
READ_D1
0x61
D2
[15:0]
WRITE_D2
0x42
READ_D2
0x62
D3
[15:0]
WRITE_D3
0x43
READ_D3
0x63
D4
[15:0]
WRITE_D4
0x44
READ_D4
0x64
D5
[15:0]
WRITE_D5
0x45
READ_D5
0x65
D6
[31:0]
WRITE_D6
0x46
READ_D6
0x66
D7
[31:0]
WRITE_D7
0x47
READ_D7
0x67
X
[23:0]
WRITE_X
0x48
READ_X
0x68
Y
[23:0]
WRITE_Y
0x49
READ_Y
0x69
SP
[23:0]
WRITE_SP
0x4A
READ_SP
0x6A
PC
[23:0]
WRITE_PC
0x4B
READ_PC
0x6B
CCR
[15:0]
WRITE_CCR
0x4C
READ_CCR
0x6C
Содержание MC9S12ZVM series
Страница 116: ...Chapter 2 Port Integration Module S12ZVMPIMV1 MC9S12ZVM Family Reference Manual Rev 1 3 116 Freescale Semiconductor ...
Страница 242: ...Chapter 7 ECC Generation Module SRAM_ECCV1 MC9S12ZVM Family Reference Manual Rev 1 3 242 Freescale Semiconductor ...
Страница 384: ...Chapter 10 Supply Voltage Sensor BATSV3 MC9S12ZVM Family Reference Manual Rev 1 3 384 Freescale Semiconductor ...
Страница 484: ...Chapter 13 Programmable Trigger Unit PTUV2 MC9S12ZVM Family Reference Manual Rev 1 3 484 Freescale Semiconductor ...
Страница 662: ...Chapter 17 Gate Drive Unit GDUV4 MC9S12ZVM Family Reference Manual Rev 1 3 662 Freescale Semiconductor ...
Страница 684: ...Chapter 18 LIN Physical Layer S12LINPHYV2 MC9S12ZVM Family Reference Manual Rev 1 3 684 Freescale Semiconductor ...
Страница 740: ...Chapter 19 128 KB Flash Module S12ZFTMRZ128K512V2 MC9S12ZVM Family Reference Manual Rev 1 3 740 Freescale Semiconductor ...
Страница 756: ...Appendix A MCU Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 756 Freescale Semiconductor ...
Страница 772: ...Appendix D LINPHY Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 772 Freescale Semiconductor ...
Страница 776: ...Appendix E GDU Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 776 Freescale Semiconductor ...
Страница 788: ...Appendix I MSCAN Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 788 Freescale Semiconductor ...
Страница 790: ...Appendix J Package Information MC9S12ZVM Family Reference Manual Rev 1 3 790 Freescale Semiconductor ...