Freescale Semiconductor MC13192, Технические данные инструкция, Страница: 3 / 22

Block Diagrams
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor 3
• Small form factor QFN-32 Package
— Meets moisture sensitivity level (MSL) 3
— 260 °C peak reflow temperature
— Meets lead-free requirements
3 Block Diagrams
Figure 3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard
802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY)
specification.
Figure 4 shows the basic system block diagram for the MC13192/MC13193 in an
application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request
line. The media access control (MAC), drivers, and network and application software (as required) reside
on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor
depending on application requirements.
4 Data Transfer Modes
The MC13192/MC13193 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1 Packet Structure
Figure 5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported.
The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.