Freescale Semiconductor e200z3, Справочное руководство

Страница: 75 / 442

Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 2-27
MCSR fields, described in Table 2-14 , indicate whether the source of a machine check condition is
recoverable. When an MCSR bit is set, the core complex asserts p_mcp_out for system information.
2.10 Software-Use SPRs (SPRG0–SPRG7 and USPRG0)
Software-use SPRs (SPRG0–SPRG7 and USPRG0, shown in Figure 2-22 ) have no defined functionality:
• SPRG0–SPRG2—Accessible only in supervisor mode.
• SPRG3—Written only in supervisor mode. It is readable in supervisor mode, but whether it can be
read in user mode depends on the implementation. It is not readable in user mode on the e200z3.
• SPRG4–SPRG7—Written only in supervisor mode. They are readable in supervisor or user mode.
• USPRG0—Accessible in supervisor or user mode.
32 33 34 35 36 37 42 43 44 58 59 60 61 62 63
Field MCP — CP_PERR CPERR EXCP_ERR — NMI
1
1
NMI bit in e200z335 only
BUS_IRERR BUS_DRERR BUS_WRERR —
Reset All zeros
R/W R/W
SPR SPR 572
Figure 2-21. Machine Check Syndrome Register (MCSR)
Table 2-14. MCSR Field Descriptions
Bits Name Description Recoverable
32 MCP Machine check input signal Maybe
33 — Reserved, should be cleared. —
34 CP_PERR Cache push parity error Unlikely
35 CPERR Cache parity error Precise
36 EXCP_ERR ISI, ITLB, or bus error on first instruction fetch for an exception handler Precise
37–42 — Reserved, should be cleared. —
43 NMI Non-maskable interrupt input signal (e200z335 only) Maybe
44–58 — Reserved, should be cleared. —
59 BUS_IRERR Read bus error on Instruction fetch Unlikely
60 BUS_DRERR Read bus error on data load Unlikely
44–60 — Reserved, should be cleared. —
61 BUS_WRERR Write bus error on buffered store or cache line push Unlikely
62–63 — Reserved, should be cleared. —