Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 2-21
2.8.1.4 Critical Save/Restore Register 1 (CSRR1)
CSRR1, shown in Figure 2-14 , is used to save and restore machine state during critical interrupts. MSR
contents are placed into CSRR1. When rfci executes, the contents of CSRR1 are restored into MSR.
CSRR1 bits that correspond to reserved MSR bits are also reserved. (See
Section 2.4.1, “Machine State
Register (MSR) .”) CSRR0 and CSRR1 are not affected by rfi or rfdi. Reserved MSR bits can be altered
by rfi, rfci, or rfdi.
2.8.1.5 Data Exception Address Register (DEAR)
DEAR, shown in Figure 2-15 , is loaded with the effective address of a data access (caused by a load, store,
or cache management instruction) that results in an alignment, data TLB miss, or data storage interrupt.
.
2.8.1.6 Interrupt Vector Prefix Register (IVPR)
The IVPR, shown in Figure 2-16 , is used during interrupt processing to determine the starting address for
the software interrupt handler. The value contained in the vector offset field of the IVOR selected for a
particular interrupt type is concatenated with the value in the IVPR to form an instruction address from
which execution is to begin.
32 63
Field Next instruction address
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 58
Figure 2-13. Critical Save/Restore Register 0 (CSRR0)
32 63
Field MSR state information
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 59
Figure 2-14. Critical Save/Restore Register 1 (CSRR1)
32 63
Field Exception address
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 61
Figure 2-15. Data Exception Address Register (DEAR)