External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
7-20
Freescale Semiconductor
7.3.1
Processor State Signals
describes the processor state signals.
p_pid0_updt
O
PID0 update. Indicates that PID0 is being updated by an
mtspr
.
State
Meaning
Asserted—PID0 is being updated by an
mtspr
.
Negated—PID0 is not being updated by an
mtspr
.
Timing
Assertion—asserts during the clock cycle the
p_pid0[0:7] outputs are changing
.
p_sysvers[0:31
]
I
System version. Core version number reflected in the SVR. See
Section 2.4.4, “System Version Register
(SVR).”
Timing
Intended to remain in a static condition and not internally synchronized.
p_pvrin[16:31]
I
Processor version. Provide a portion of the version number for a particular CPU. Reflected in the PVR.
See
Section 2.4.3, “Processor Version Register (PVR).”
Timing
Intended to remain in a static condition and are not internally synchronized.
Table 7-15. Descriptions of Processor State Signals
Signal
I/O
Signal Description
p_pstat[0:6]
O
Processor status. Indicate the internal execution unit status. Any values not shown are reserved.
p_pstat[0:6]
Internal Processor Status
00000xx
Execution stalled
00001xx
Execute exception
00010xx
Instruction squashed
01000xx
Processor in halted state
01001xx
Processor in stopped state
01010xx
Processor in debug mode
1
01011xx
Processor in checkstop state
10000sm
Complete instruction
2,3
1000100
Complete
lmw
or
stmw
1000101
Complete
e_lmw
or
e_stmw
1001000
Complete
isync
1001011
Complete
se_isync
100110m
Complete
lwarx
or
1100000
Complete branch instruction
bc
,
bcl
,
bca
,
bcla, b, bl, ba, bla
resolved as not taken
1100001
Complete branch instruction
e_bc
,
e_bcl
,
e_b, e_bl
resolved as not taken
1100011
Complete branch instruction
se_bc
,
se_bcl
,
se_b, se_bl
resolved as not taken
1100100
Complete branch instruction
bc
,
bcl
,
bca
,
bcla, b, bl, ba, bla
resolved as taken
1100101
Complete branch instruction
e_bc
,
e_bcl
,
e_b, e_bl
resolved as taken
1100111
Complete branch instruction
se_bc
,
se_bcl
,
se_b, se_bl
resolved as taken
1101000
Complete
bclr
,
bclrl, bcctr
,
bcctrl
resolved as not taken
1101100
Complete
bclr
,
bclrl, bcctr
,
bcctrl
resolved as taken
1101111
Complete
se_blr
,
se_blrl, se_bctr
,
se_bctrl
(always taken)
111000m
Complete
isel
with condition false
111010m
Complete
isel
with condition true
1111100
Complete
rfi
,
rfci
, or
rfdi
1111111
Complete
se_rfi
,
se_rfci
, or
se_rfdi
Timing
Synchronous with
m_clk, so the indicated status may not apply to a current bus transfer.
Table 7-14. Descriptions of Miscellaneous Processor Signals (continued)
Signal
I/O
Signal Description
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