Freescale Semiconductor e200z3, Справочное руководство

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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 6-23
6.7.1.2 SPE Load and Store Instruction Timing
Instruction timing for SPE load and store instructions is shown in Table 6-4 . The table is sorted by opcode.
Actual timing depends on alignment; the table indicates timing for aligned operands.
evrlwi 1 1
evrndw 1 1
evsel 1 1
evslw 1 1
evslwi 1 1
evsplatfi 1 1
evsplati 1 1
evsrwis 1 1
evsrwiu 1 1
evsrws 1 1
evsrwu 1 1
evsubfw 1 1
evsubifw 1 1
evxor 1 1
Table 6-5. SPE Load and Store Instruction Timing
Instruction Latency Throughput Comments
evldd 1 1
evlddx 1 1
evldh 1 1
evldhx 1 1
evldw 1 1
evldwx 1 1
evlhhesplat 1 1
evlhhesplatx 1 1
evlhhossplat 1 1
evlhhossplatx 1 1
evlhhousplat 1 1
evlhhousplatx 1 1
evlwhe 1 1
Table 6-4. Timing for Integer Simple Instructions (continued)
Instruction Latency Throughput Comments