Freescale Semiconductor e200z3, Справочное руководство

Страница: 234 / 442

Memory Management Unit
e200z3 Power Architecture Core Reference Manual, Rev. 2
5-12 Freescale Semiconductor
• Loading of the data exception address register (DEAR) with the EA of the load, store, or cache
management instruction that caused an alignment, data TLB miss, or data storage interrupt.
• The tlbwe instruction. When tlbwe is executed, the new TLB entry contained in MAS0–MAS2 is
written into the TLB.
5.5.2 Reading the TLB
The TLB array can be read by first writing the necessary information into MAS0 using mtspr and then
executing the tlbre instruction. To read an entry from TLB1, MAS0[TLBSEL] must be set to 01 and
MAS0[ESEL] must be set to point to the desired entry. After tlbre executes, MAS1–MAS3 are updated
with the data from the selected TLB entry. See
Section 5.4, “Software Interface and TLB Instructions.”
5.5.3 Writing the TLB
The TLB1 array can be written by first writing the necessary information into MAS0–MAS3 using mtspr
and then executing the tlbwe instruction. To write an entry into TLB1, the TLBSEL field in MAS0 must
be set to 01, and the ESEL bits in MAS0 must be set to point to the desired entry. When the tlbwe
instruction is executed, the TLB entry information stored in MAS1–MAS3 is written into the selected TLB
entry. See
Section 5.4, “Software Interface and TLB Instructions.”
5.5.4 Searching the TLB
TLB1 can be searched using a tlbsx by first writing the necessary information into MAS6. The tlbsx
instruction searches using EPN[0–19] from the GPR selected by the instruction, SAS (search AS bit) in
MAS6, and SPID in MAS6. If the search is successful, the given TLB entry information is loaded into
MAS0–MAS3. The valid bit in MAS1 is used as the success flag. If the search is successful, the valid bit
in MAS1 is set; if unsuccessful, it is cleared. The tlbsx instruction is useful for finding the TLB entry that
caused a data or instruction storage interrupt. See
Section 5.4, “Software Interface and TLB Instructions.”
5.5.5 TLB Coherency Control
The e200z3 core provides the ability to invalidate a TLB entry as described in the Book E PowerPC
architecture. The tlbivax instruction invalidates local TLB entries only. No broadcast is performed, as no
hardware-based coherency support is provided.
The tlbivax instruction invalidates by effective address only. This means that only the TLB entry’s EPN
bits are used to determine if the TLB entry should be invalidated. Therefore, a single tlbivax can invalidate
multiple TLB entries, because the AS and TID fields of the entries are ignored.
5.5.6 TLB Miss Exception Update
When a TLB miss exception occurs, MAS0–MAS3 are updated with the defaults specified in MAS4 and
the AS and EPN[0–19] of the access that caused the exception. In addition, the ESEL bits are updated with
the replacement entry value. This sets up all the TLB entry data necessary for a TLB write except for the
RPN[0–19], the U0–U3 user bits, and the UX/SX/UW/SW/UR/SR permission bits, all of which are stored
in MAS3. Thus, if the defaults stored in MAS4 are applicable to the TLB entry to be loaded, the TLB miss