Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 2-63
The MMUCFG fields are described in Table 2-29 .
2.16.3 TLB Configuration Registers (TLB n CFG)
The TLBnCFG read-only registers provide information about each specific TLB that is visible to the
programming model.
2.16.3.1 TLB Configuration Register 0 (TLB0CFG)
TLB0CFG, shown in Figure 2-45 , provides information about the configuration of TLB0. Because the
e200z3 MMU design does not implement TLB0, this register reads as all zeros. It is supplied to allow
software to query it in a way compatible with other Freescale Book E designs.
The TLB0CFG fields are described in Table 2-30 .
Table 2-29. MMUCFG Field Descriptions
Bits Name Description
32–48 — Reserved, should be cleared.
49–52 NPIDS Number of PID registers.
0001 This version of the MMU implements one PID register (PID0).
53–57 PIDSIZE PID register size.
00111PID registers contain 8 bits in this version of the MMU.
58–59 — Reserved, should be cleared.
60–61 NTLBS Number of TLBs.
01 This version of the MMU implements two TLB structures: a null TLB0 and a populated TLB1.
62–63 MAVN MMU architecture version number.
00 This version of the MMU implements version 1.0 of the Freescale Book E MMU architecture.
32 39 40 43 44 47 48 49 50 51 52 63
Field ASSOC MINSIZE MAXSIZE IPROT AVAIL — NENTRY
Reset All zeros (TLB0 is not implemented)
R/W Read only
SPR SPR 688
Figure 2-45. TLB Configuration Register 0 (TLB0CFG)
Table 2-30. TLB0CFG Field Descriptions
Bits Name Description
32–39 ASSOC Associativity.
40–43 MINSIZE Minimum page size.
44–47 MAXSIZE Maximum page size.
0
48 IPROT Invalidate protect capability.
0