Freescale Semiconductor e200z3, Справочное руководство

Страница: 110 / 442

Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
2-62 Freescale Semiconductor
2.16 MMU Registers
This section describes the e200z3 registers for setting up and maintaining the TLBs.
2.16.1 MMU Control and Status Register 0 (MMUCSR0)
MMUCSR0, shown in Figure 2-43 , controls the state of the MMU.
The MMUCSR0 fields are described in Table 2-28 .
2.16.2 MMU Configuration Register (MMUCFG)
The MMU configuration register (MMUCFG) is a 32-bit read-only register. The SPR number for
MMUCFG is 1015 in decimal. MMUCFG, which provides information about the configuration of the
e200z3 MMU design, is shown in
Figure 2-44 .
32 61 62 63
Field — TLB1_FI —
Reset All zeros
R/W R/W
SPR SPR 1012
Figure 2-43. MMU Control and Status Register 0 (MMUCSR0)
Table 2-28. MMUCSR0 Field Descriptions
Bits Name Description
32–61 — Reserved, should be cleared.
62 TLB1_FI TLB1 flash invalidate
0 No flash invalidate
1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation, after which TLB1_FI is cleared.
Setting TLB1_FI while an invalidation operation is in progress causes an undefined operation. Clearing
TLB1_FI while an invalidation operation is in progress is ignored. TLB1 invalidation operations require 3
cycles to complete.
63 — Reserved, should be cleared.
32 48 49 52 53 57 58 59 60 61 62 63
Field — NPIDS PIDSIZE — NTLBS MAVN
Reset 0000_0000_0000_0000_0 000_1 001_11 00 01 00
R/W Read only
SPR SPR 1015
Figure 2-44. MMU Configuration Register 1 (MMUCFG)