Force SYS68K/CPU-30 R4, Техническое справочное руководство

Страница: 71 / 209

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 58
3.9 The DUSCC 68562
The Dual Universal Serial Communications Controller 68562 (DUSCC)
is a single-chip MOS-LSI communications device that provides two
independent, multiprotocol, full duplex receiver/transmitter channels in a
single package. Each channel consists of a receiver, a transmitter, a 16-bit
multifunction counter/timer, a digital phase locked loop (DPLL), a
parity/CRC generator and checker, and associated control circuits.
3.9.1 Features of the
DUSCC - Dual full-duplex synchronous/asynchronous receiver and
transmitter
- Multiprotocol operation consisting of:
BOP: HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link
level
COP: BISYNC, DDCMP, X.21
ASYNC: 5-8 bit plus optional parity
- Programmable data encoding formats: NRZ, NRZI, FM0, FM1,
Manchester
- 4 character receiver and transmitter FIFOs
- Individual programmable baud rate for each receiver and
transmitter
- Digital phase locked loop
- User programmable counter/timer
- Programmable channel modes full/half duplex, auto echo, local
loopback
- Modem control signals for each channel: RTS, CTS, DCD
- CTS and DCD programmable auto enables for receiver and
transmitter
- Programmable interrupt on change of CTS or DCD