Rev AN-2153 REV B
©2016 Finisar Corporation AN-2153 REV B
Page 3 of 6
20-May-2016
SFF-8636 Table 6-34 Page 03h Bytes 234-235
Transmitter Input Equalization
Nominal
Units
11xx
Reserved
1011
Reserved
1010
10
dB
1001
9
dB
1000
8
dB
0111
7
dB
0110
6
dB
0101
5
dB
0100
4
dB
0011
3
dB
0010
2
dB
0001
1
dB
0000
0
No Eq
Manual
– fixed programmable CTLE
In this method the equalization is fixed for each channel, and the optimum setting can be programmed
based on the loss characteristics of the high speed electrical interface. The host has I2C write access to
bytes 234-235 and can program the equalization based on the amount of gain needed to correct for the
channel impairments. These registers are volatile and so any non-default register value will need to be
written upon each module power cycle or reset.
Initialization Process in fixed programmable CTLE mode:
In manual CTLE mode, we recommend that the host follow the initialization sequence described below:
1.
Host board is powered on and initialized. The QSFP28 module may or may not already be
plugged into the host board. Host should implement low power mode (LPMode pin 31, active
High)and hold the module in reset (RESETL pin 9 active low)
2.
The host PHY is enabled and configured to the settings that meet the host compliance point
TP1.
3.
Host brings up the MAC/PCS interface, and CAUI-4 idle packets are transmitted.
4.
If not already present in step 1, the QSFP28 module is hot plugged into host.
5.
The host releases RESET, and allows 2 seconds for the module to be ready to communicate
over the I2C.
6.
QSFP28 module is held in Tx disable state by setting Byte 86 to value 0x0F
