Figure 14. Reference circuit of the PCM interface external Codec chip
5.8. PCIe Interface
FM101-CG
module supports a group of PCIe GEN 2.0 x 1 lanes.
Table 23. PCIe pin definition
Pin Name
I/O
Pin
Number
Description
PETn0
DO
41
PCIe data transmitting signal negative
PETp0
DO
43
PCIe data transmitting signal positive
PERn0
DI
47
PCIe Data receiving signal negative
PERp0
DI
49
PCIe Data receiving signal positive
PERST#
DI
50
PCIe mode reset signal
CLKREQ#
DIO
52
PCIe clock request signal with
external pull-up
REFCLKN
DIO
53
PCIe reference clock signal negative
PEWAKE#
DO
54
PCIe RC mode wake-up signal with
external pull-up
REFCLKP
DIO
55
PCIe reference clock signal positive
5. Functional Interface
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