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FIBOCOM FG621-LA Series Hardware Guide
Page 39 of 57
insertion at low level.
Figure 5-15 FG621-LA SD reference circuit
5.10 SPI Interface
The FG150-AE module supports 1 SPI interface, works in master mode, and the clock supports up to
50MHz.
Table 5-18 SPI interface definition
Pin Name
I/O
Pin#
Description
SPI_MOSI
77
DO
SPI output signal
SPI_MOSI
78
DI
SPI input signal
SPI_CS
79
DO
SPI Chip Selection signal
SPI_CLK
80
DO
SPI clock signal
5.11 GPIO Interface
FG621-AE-00 module reserves five GPIO interfaces for clients, with a voltage domain of 1.8V. Clients can
use the interfaces as needed and simply leave them floating when not in use. GPIO pin definition is
shown in the following table:
Table 5-19 GPIO pin definition
Pin Name
I/O
Pin#
Description
Instructions for Use
GPIO_1
IO
138
General-Purpose
I/O
Port 1
Input pull-down inside the
chip by default
GPIO_2
IO
139
General-Purpose
I/O Input pull-down inside the
