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FIBOCOM FG621-LA Series Hardware Guide
Page 35 of 57
Since the module supports USB 2.0 High-Speed, TVS equivalent capacitance on the USB_DM/DP
differential signal line is required to be less than 1pF, and a 0.5pF TVS is recommended. It is
recommended to connect a 0Ω resistor to USB_DM/DP differential line in series.
USB_DM and USB_DP are high-speed differential signal lines, which can achieve the maximum
transmission rate of 480Mbits/s, and must follow the rules below in PCB Layout:
The impedance of USB_DM and USB_DP signal line should be controlled in 90Ω.
USB_DM and USB_DP signal lines shall be parallel and equal in length, and avoid the
right-angle route.
USB_DM and USB_DP signal lines are routed on the signal layer closest to the ground layer,
and the lines shall be grounded.
5.5 UART Interface
FG621-LA series module provides debug serial port, which supports 115200bps baud rate for debugging
and problem analysis. The following table is the description of debug serial port pins:
Table 5-10 Pin definition of debug serial port
5.6 ADC Interface
FG621-LA series module supports two-channel ADC interface, 12 bit. The use of AT+MMAD command
can read the value of ADC interface. The voltage range of ADC interface is 0V~1.2V.
Table 5-11 ADC pin definition
Pin Name
I/O
Pin#
Description
ADC0
AI
173
Analog to digital converter interface 0
ADC1
AI
175
Analog to digital converter interface 1
Note:
Ground isolation is recommended for ADC layout to improve ADC voltage measurement
accuracy.
5.7 I2C Interface
FG621-LA series module supports one I2C interface, applying the standard I2C Specification, version 3.0.
The I2C signal has been pulled up inside the chip, so there is no need to pull it up outside.
Table 5-12 I2C pin definition
Pin Name
I/O
Pin#
Description
DBG_RXD
DI
136
Module Receive data
DBG_TXD
DO
137
Module Transmit data