Functional Description
CPC805
C P C 8 0 5 U s e r M a n u a l
39
© 2 0 1 2 F a s t w e l v . 0 0 1 a E P r e
2.4
Timers
CPC805 is equipped with the following timers:
¢
RTC – Real-Time Clock
ICH contains a real-time clock. The RTC includes 256 bytes of battery-backed CMOS RAM.
The RTC features include timekeeping with alarm function and 100-year calendar. A coin-cell
battery powers the real-time clock and CMOS memory.
¢
Counter/Timer
Three 8254-type counters/timers are available on the CPC805.
¢
Watchdog Timer
2.4.1
Watchdog Timer
Programmable the watchdog timer is realized in FPGA and an LPC bus device. WDT is enabled
and IRQ is selected in BIOS Setup.
WDT consists of the counter register [Timer Current Value Register] decremented with 32.768 KHz
frequency, and initial value register [Timer Initial Value Register]. It is possible to set the timeout
period from 0 to 512 seconds with increments of 30.52
m
s by changing the value in this register.
On zeroing the counter either an interrupt is generated or the Reset of the module occurs on
double zeroing.
By default, WDT is inactive. The equation below can be used to calculate the timeout T
WD
in
m
s as
a function of the decimal value in the WD register (K
WD
):
T
WD
[
m
s
] = K
WD
* 10
6
/ 2
15
For example, decimal value "1" of K
WD
(000001h) corresponds to the timeout of 30.52
m
s, and
K
WD
= 16777215 (FFFFFFh) – 512 seconds.
WDT is reset in different ways:
1) Write any value to the counter register [Timer Current Value Register]
2) Write any value to 80h port (the mode is enabled in BIOS Setup and is active only if access
cycles to the port 80h are translated to LPC bus.)
After the first expiry of the timeout the TMF flag is set, after the second timeout expiry – STF flag.
WDT is controlled via I/O registers:
1) Stop countdown
2) Write the timeout value to [Timer Initial Value Register]
3) Initialize the WDT register by any of the reset methods (i.e. by writing any value to [Timer
Current Value Register]). This leads to wring the initial value from [Timer Initial Value Register] to
[Timer Current Value Register].
4) Start decrementing the counter and, if necessary, enable auto reset of the module.
5) Then, with a period less than timeout perform regular strobing of the WDT. In case WDT was
not srobed, TMF flag is set after first timeout expiry and an interrupt occurs. After the second
timeout expiry STF flag is set and the second interrupt is issued or the module will be Reset if this
is enabled.
