VULCAN Technical Manual
Detailed hardware description
© 2007 Eurotech Ltd Issue D
22
PCI bus
The IXP425 network processor PCI interface is a 32 bit 66MHz / 33MHz PCI controller
and PCI bus compatible with PCI v2.2 specification. The PCI controller on VULCAN is
configured to operate at 33MHz as a host, with internal built-in PCI arbiter and PCI
initiator capabilities. 33MHz clock distribution for PCI based devices and the
processor’s expansion bus interface are implemented using the GPIO15 clock output
of the IXP425 processor and the zero-delay clock buffer.
The Initialization Device SELect (IDSEL) signals of each of the PCI devices are
mapped to the PCI address and data bus (PCI_AD) signals as shown in the table
below. The corresponding PCI device is selected if the PCI address and data bus
signal mapped to the particular PCI device IDSEL signal is asserted.
Device
IDSEL signal
PCI interrupt mapping
USB 2.0 host controller
PCI_AD31
USB_INTA#
GPIO2
CardBus controller
PCI_AD30
CF_INTB#
GPIO3
PCI bus devices can be reset using bit 4 of WD setup register. The register is memory
mapped and located on the expansion bus (CS5#). The following table shows the WD
setup register bit definitions:
Bits Description
7:5 Not
used.
4
PCI_RST#: When zero, resets PCI bus. Set to one if not used.
3
WDI: Watchdog Input. If WDI remains either high or low for the
duration of the watchdog timeout period (t
WD
), WDT triggers a reset
pulse. The internal watchdog timer clears whenever a reset pulse
is asserted or whenever WDI sees a rising or falling edge.
2:0
WDSET[2:0] - watchdog timeout period setup bits.
Hex Offset Address:
0x05000000
Reset Hex Value:
0x1B
Access:
Read/write
Bits 0-3 of WD setup register are used to configure external Watch Dog Timer.
When writing to this register make sure that you mask bits [0-3].
