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Soft Power Management Registers 30
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address 602h
(ACPI PM1a_EVT_BLK) Attribute R/W
Default Value 0000h
Size 16-bit
Lockable No
Usage ACPI
Power Well Bits 0–7: Core,
Bits 8–15: RTC
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register
should be cleared to 0 based on a Power Button Override. The resume well bits are all cleared by
RSMRST#. The RTC sell bits are cleared by RTCRST#.
Bit Description
15:12 Reserved.
11 PME# Enable (PME_EN)—R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1–S4
state or from S5 (if entered via SLP_EN, but not power button override).
10 ICH2 (82801BA):
Reserved
9 Reserved
8 RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by
RSMRST# or a CF9h write. Assertion of RTCRST# resets this bit.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7 Reserved
6 TCO SCI Enable (TCOSCI_EN)—R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
5 AC97 Enable (AC97_EN)—R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
4 USB Controller 2 Enable (USB2_EN)—R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
3 USB Controller 1 Enable (USB1_EN)—R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
2 Thermal Pin Polarity (THRM#_POL)—R/W. This bit controls the polarity of the THRM# pin needed to set the THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
1 Reserved
0 Thermal Signal Reporting Enable (THRM_EN)—R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
An0065. CPU-1450 Soft Power Management
Table 13. GPE0_EN—General Purpose Event 0 Enables Register