Eurotech CPU-1450, Руководство пользователя, Страница: 28 / 43

Soft Power Management Registers 28
PM1_EN—Power Management 1 Enable Register
I/O Address 6002h
(ACPI PM1a_EVT_BLK) Attribute R/W
Default Value 0000h
Size 16-bit
Lockable No
Usage ACPI or Legacy
Power Well Bits 0–7: Core,
Bits 8–15: Resume
Bit Description
15:11 Reserved.
10 RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event to wake after
a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override
event.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active.
8 Power Button Enable (PWRBTN_EN)—R/W. This bit is used to enable the setting of the
PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect
on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is
always enabled as a Wake event.
0 = Disable.
1 = Enable.
5 Global Enable (GBL_EN)—R/W. When both the GBL_EN and the GBL_STS are set, an SCI is
raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
0 Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with the SCI_EN bit as
described below:
TMROF_EN SCI_EN Effect when TMROF_STS is set
0 x No SMI# or SCI
1 0 SMI#
1 1 SCI
An0065. CPU-1450 Soft Power Management
Table 11. PM1_EN—Power Management 1 Enable Register