
XETK-V1.0 - User’s Guide
30
ETAS
Hardware Description
4.12
Braindead Flashing
Braindead Flashing (BDF) means downloading program code to the non-volatile
memory of the ECU (i.e. internal or external flash), regardless of the current
memory contents. It is not required that a programming routine is present in the
ECU - the memory may be empty or corrupted.
The XETK-V1.0 suppots Braindead Flashing via Nexus (JTAG) debug interface for
all MPC5500 family microcontrollers. It is recommended as standard method for
all new projects.
4.12.1
Braindead Flashing via Nexus (JTAG) Debug Interface
This method uses the Nexus (JTAG) interface of the MCU's microcontroller to
enable the debug mode of microcontroller and to download a flash program-
ming driver into the microcontroller's internal SRAM.
After download, the microcontroller is given a resume/go command. It executes
the programming driver which receives data via the ETK mailbox and programs it
into the microcontroller's flash. When flash programming is done, a reset is
issued and the microcontroller executes the recently programmed code.
The following steps are sequenced by a ProF control flow:
• Put ECU's microcontroller into reset
• Disable external watchdog timer (optional, see chapter 4.12.2
• Initiate microcontroller's debug mode and halt state
• Initialize the Internal SRAM
• Initialize the MMU registers to a known state
• Download flash programming driver into the internal RAM region of the
controller that contains communication and flash routines
• Set Program Counter to point to the beginning of the boot code
• Resume microcontroller code execution by issuing a go/resume command
• Program the new ECU software to the non-volatile memory (internal or
external flash)
• Reset the CPU (release Nexus (JTAG) debug interface control)
CAUTION!
During Braindead Flashing via Nexus (JTAG), external debugger
should be removed.
Note
When flashing an MPC5534 microcontroller, please ensure that your flash pro-
gramming driver sets the Nexus (JTAG) access priority to internal SRAM higher
than the priority for opcode fetches from internal SRAM (MPC5534 Crossbar
register
XBAR_MPR3
). ETAS suggests to set
XBAR_MPC3
to the value
0x00000213
. When using the default priority for Nexus (JTAG) accesses, the
ProF flow may fail as the ETK does not always gets access to the microcontrol-
lers SRAM. See the MPC5534 reference manual section XBAR for details.