ETAS ETK-V1.1, Руководство пользователя

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ETK-V1.1 - User’s Guide 40
ETAS Technical Data
7.10.1 Read Timing: Data Emulation and Measurement Data DPR
Fig. 7-1 Read Cyle: Data Emulation and Measurement Data DPR
7.10.2 Write Timing: Data Emulation and Measurement Data DPR
.
Fig. 7-2 Write Cycle: Data Emulation and Measurement Data DPR
Para. Description Min Max Unit
t
1
Address access time 19 ns
t
2
Chip select access time 23 ns
t
3
Output enable until valid data is driven to bus 22 ns
t
4
Valid data is driven to bus after output enable
inactive 4 10 ns
t
5
Time after read until other device may drive bus 15 ns
Para. Description Min Max Unit
t
1
Address valid before write enable becomes active 0 ns
t
2
Address valid before end of write 5 ns
t
3
Address valid after end of write 5 ns
t
4
Data valid before end of write 3 ns
t
5
Data valid after end of write 5 ns
t
6
Write enable pulse width 9 ns
0ns 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns
ADDR[12:30]
CS[3:0]
OE
DATA[15:0]
Address
Data
t1
t2
t3
t4
t5
0ns 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns
ADDR[12:30]
CS[3:0]
RD/WR
WE[1:0]
DATA[15:0]
Address
Data
t1
t2
t3
t4 t5
t6