ETAS
Technical Data
BR_XETK-S4.0
-
User
Guide
45
7.7
Microcontroller Interface
7.8
Power-on Delay of ECU Reset
Symbol
Condition
Min
Typ
Max Unit
ECU Standby
RAM Output
Voltage
VDDSTBY Max 500 mA load 0.94
0.999 1.04 V
VDDPSTBY
Output Voltage
VDDP
-
STBY
Max 80 mA load 3.14
3.3
3.46 V
CAL_Wakeup
Output Voltage
CAL_WAK
EUP
U
Batt
= 6.0 - 36 V;
load = 0 - 50 mA
U
Batt
-1V
U
Batt
V
ECU Power Sup
-
ply Supervision
Voltage
(3.3 V selected)
VDDP
ECU on
2.70
2.80
2.89 V
ECU off
2.44
2.54
2.66 V
IDDP
VDDP 3.3 V
200
A
ECU Standby
RAM Supervi
-
sion Voltage
VDDSTBY
/VDDST
-
BY_SENSE
VDDSTBY
0.86
0.89
0.92 V
VDDSTBY
0.85
0.88
0.91 V
IDDSTBY
VDDSTBY 0.95 V
73
A
Parameter
Symbol Condition
Min Typ
Max Unit
Reset delay 1
1)
t
Reset1
U
Batt
= 12
V
ECU_VDDP goes
high
3
5
20
ms
Reset delay 2
2)
t
Reset2
U
Batt
goes high
100
240 ms
1)
Delay of ECU reset through ETK without transferring the FPGA (U
Batt
pres
-
ent, VDDP will be switched on)
2)
max. delay of ECU reset through ETK (U
Batt
and VDDP will be switched on)
