Technical Data
5.3 CAN Interface
Number of CAN
interfaces
4
CAN controller
esdACC in FPGA Spartan® 3e,
acc. to ISO 11898-1 (CAN 2.0 A/B)
CAN protocol
according to ISO 11898-1
Physical Layer
High-speed CAN interface according to ISO 11898-2,
bit rate up to 1 Mbit/s
Electrical isolation
via digital isolator and DC/DC converter,
500 V (effective) between CAN potential and module-system-potential
with pollution degree 1
Bus termination
terminating resistor has to be set externally, if required
Connector
DSUB25 (male)
Table 5:
Data of the CAN interface
5.4 CompactPCI Bus
Host bus
PCI-Bus according to PCI Local Bus Specification 2.2
PCI-data/address bus 32 Bit, 33/66 MHz
Microprocessor
optional 32-bit µC in FPGA (MicroBlaze)
Board dimension
according to CompactPCI-Specification, Rev. 2.2
Connector
Connector coding
Universal-Board, not keyed
(3.3 V or 5 V signalling voltage)
Table 6:
Data of the CompactPCI bus
5.5 IRIG-B Interface (Option)
Number
1x analog and 1x RS-422 compatible (via front panel, both electrically
isolated),
1x RS-422 compatible (at J2 only)
Controller
8051 microcontroller
Connector
DSUB25
Table 7:
Data of the serial interface
CPCI-CAN/400-4
Hardware Manual • Doc. No.: C.2033.21 / Rev. 1.2
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