Epson S1C33 Series, Руководство по основам

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2 REGISTERS
S1C33 FAMILY C33 PE CORE MANUAL EPSON 5
2 . 3 Processor Status Register (PSR)
Symbol
PSR
Size
32 bits
Initial value
0x00000000
Register name
Processor Status Register
R/W
R/W
The Processor Status Register (hereinafter referred to as the “ PSR ” ) is a 32 -bit register for storing the internal status
of the processor.
The PSR stores the internal status of the processor when the status has been changed by instruction execution. It is
referenced in arithmetic operations or branch instructions, and therefore constitutes an important internal status in
program composition. The PSR can be altered by a program.
As the PSR affects program execution, whenever an interrupt or exception occurs, the PSR is saved to the stack,
except for debug exceptions, to maintain the PSR value. The IE flag (bit
4 ) in it is cleared to 0 . The
reti
instruction is used to return from interrupt handling, and the PSR value is restored from the stack at the same time.
IL[3:0] –
7 8 9 10 11
–
6
–
5
IE
4
C
3
V
2
Z
1
N
0
–
31 12
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Initial value
R/W . . . . . 0
R
Figure 2 . 3 . 1 Processor Status Register (PSR)
The dash “ – ” in the above diagram indicates unused bits. Writing to these bits has no effect, and their value when
read out is always 0 .
IL[ 3 : 0 ] (bits 11 – 8 ): Interrupt Level
These bits indicate the priority levels of the processor interrupts. Maskable interrupt requests are accepted only
when their priority levels are higher than that set in the IL bit field. When an interrupt request is accepted, the
IL bit field is set to the priority level of that interrupt, and all interrupt requests generated thereafter with the
same or lower priority levels are masked, unless the IL bit field is set to a different level or the interrupt handler
routine is terminated by the
reti
instruction.
IE (bit 4 ): Interrupt Enable
This bit controls maskable external interrupts by accepting or disabling them. When IE bit = 1 , the processor
enables maskable external interrupts. When IE bit = 0 , the processor disables maskable external interrupts.
When an interrupt or exception is accepted, the PSR is saved to the stack and this bit is cleared to 0 . However,
the PSR is not saved to the stack for debug exceptions, nor is this bit cleared to 0 .
C (bit 3 ): Carry
This bit indicates a carry or borrow. More specifically, this bit is set to 1 when, in an add or subtract instruction
in which the result of operation is handled as an unsigned 32 -bit integer, the execution of the instruction
resulted in exceeding the range of values representable by an unsigned 32 -bit integer, or is reset to 0 when the
result is within the range of said values.
The C flag is set under the following conditions:
( 1 ) When an addition executed by an add instruction resulted in a value greater than the maximum value
0 xFFFFFFFF representable by an unsigned 32 -bit integer
( 2 ) When a subtraction executed by a subtract instruction resulted in a value smaller than the minimum value
0 x 00000000 representable by an unsigned 32 -bit integer
V (bit 2 ): OVerflow
This bit indicates that an overflow or underflow occurred in an arithmetic operation. More specifically, this bit
is set to
1 when, in an add or subtract instruction in which the result of operation is handled as a signed 32 -bit
integer, the execution of the instruction resulted in an overflow or underflow, or is reset to 0 when the result of
the add or subtract operation is within the range of values representable by a signed 32 -bit integer. This flag is
also reset to 0 by executing a logical operation instruction.