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aPPenDiX a liST OF i/O ReGiSTeRS
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
aP-a-29
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
T16a
Comparator/
Capture Ch.1
interrupt enable
Register
(T16a_ien1)
0x542a
(16 bits)
D15–6 –
reserved
–
–
–
0 when being read.
D5
CaPBOWie Capture B overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D4
CaPaOWie Capture A overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D3
CaPBie
Capture B interrupt enable
1 Enable
0 Disable
0
R/W
D2
CaPaie
Capture A interrupt enable
1 Enable
0 Disable
0
R/W
D1
CBie
Compare B interrupt enable
1 Enable
0 Disable
0
R/W
D0
Caie
Compare A interrupt enable
1 Enable
0 Disable
0
R/W
T16a
Comparator/
Capture Ch.1
interrupt Flag
Register
(T16a_iFlG1)
0x542c
(16 bits)
D15–6 –
reserved
–
–
–
0 when being read.
D5
CaPBOWiF Capture B overwrite interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D4
CaPaOWiF Capture A overwrite interrupt flag
0
R/W
D3
CaPBiF
Capture B interrupt flag
0
R/W
D2
CaPaiF
Capture A interrupt flag
0
R/W
D1
CBiF
Compare B interrupt flag
0
R/W
D0
CaiF
Compare A interrupt flag
0
R/W
0xffff84–0xffffd0
S1C17 Core i/O
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
Processor iD
Register
(iDiR)
0xffff84
(8 bits)
D7–0 iDiR[7:0]
Processor ID
0x10: S1C17 Core
0x10
0x10
R
Debug RaM
Base Register
(DBRaM)
(S1C17624/604/
602)
0xffff90
(32 bits)
D31–24 –
Unused (fixed at 0)
0x0
0x0
R
D23–0 DBRaM[23:0] Debug RAM base address
S1C17624/604: 0x1fc0
S1C17602: 0x0fc0
←
R
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
iBe4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
iBe3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
iBe2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
iBe1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
iBe0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
Se
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
instruction
Break address
Register 1
(iBaR1)
0xffffb4
(32 bits)
D31–24 –
reserved
–
–
–
0 when being read.
D23–0 iBaR1[23:0] Instruction break address #1
IBAR123 = MSB
IBAR10 = LSB
0x0 to 0xffffff
0x0 R/W
instruction
Break address
Register 2
(iBaR2)
0xffffb8
(32 bits)
D31–24 –
reserved
–
–
–
0 when being read.
D23–0 iBaR2[23:0] Instruction break address #2
IBAR223 = MSB
IBAR20 = LSB
0x0 to 0xffffff
0x0 R/W
instruction
Break address
Register 3
(iBaR3)
0xffffbc
(32 bits)
D31–24 –
reserved
–
–
–
0 when being read.
D23–0 iBaR3[23:0] Instruction break address #3
IBAR323 = MSB
IBAR30 = LSB
0x0 to 0xffffff
0x0 R/W
instruction
Break address
Register 4
(iBaR4)
0xffffd0
(32 bits)
D31–24 –
reserved
–
–
–
0 when being read.
D23–0 iBaR4[23:0] Instruction break address #4
IBAR423 = MSB
IBAR40 = LSB
0x0 to 0xffffff
0x0 R/W