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24 a/D COnVeRTeR (aDC10)
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
24-3
3.1.1 A/D Conversion Clock (PCLK Division Ratio) Selection
Table 24.
aDDF[3:0]
Division ratio
0xf
Reserved
0xe
1/32768
0xd
1/16384
0xc
1/8192
0xb
1/4096
0xa
1/2048
0x9
1/1024
0x8
1/512
0x7
1/256
0x6
1/128
0x5
1/64
0x4
1/32
0x3
1/16
0x2
1/8
0x1
1/4
0x0
1/2
(Default: 0x0)
Selecting a/D Conversion Start and end Channels
24.3.2
Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have been
set for analog input. To enable A/D conversions in multiple channels to be performed successively through one con-
vert operation, specify the conversion start and conversion end channels using ADCS[2:0]/ADC10_TRG register
and ADCE[2:0]/ADC10_TRG register, respectively.
3.2.1 Relationship between ADCS/ADCE and Input Channels
Table 24.
aDCS[2:0]/aDCe[2:0]
Channel selected
0x7
AIN7
0x6
AIN6
0x5
AIN5
0x4
AIN4
0x3
AIN3
0x2
AIN2
0x1
AIN1
0x0
AIN0
(Default: 0x0)
Example: Operation of one A/D conversion
ADCS[2:0] = 0, ADCE[2:0] = 0
Converted only in AIN0
ADCS[2:0] = 0, ADCE[2:0] = 3
Converted in the following order: AIN0
→
AIN1
→
AIN2
→
AIN3
ADCS[2:0] = 2, ADCE[2:0] = 1
Converted in the following order: AIN2
→
AIN3
→
AIN4
→
AIN5
→
AIN6
→
AIN7
→
AIN0
→
AIN1
a/D Conversion Mode Setting
24.3.3
The A/D converter provides two conversion modes that can be selected using ADMS/ADC10_TRG register: one-
time conversion mode and continuous conversion mode.
1. One-time conversion mode (aDMS = 0)
The A/D converter performs A/D conversion for all analog inputs within the range from the start channel speci-
fied by ADCS[2:0]/ADC10_TRG register to the end channel specified by the ADCE[2:0]/ADC10_TRG register
once and then stops automatically.