Epson MF1436-02, Руководство пользователя

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18
EPSON
S5U1C63000H2 MANUAL
(S1C63 FAMILY IN-CIRCUIT EMULATOR)
CHAPTER 5: OPERATION AND FUNCTION OF S5U1C63000H2
(7) Register (data) break
The register (data) value after completion of the break operation may differ from the original setting
register (data) condition for the break. For instance, in the timing chart to set sequentially 5 and 6 into
the A register, if the A register is 5 as a register break condition;
ld %a, 5 ld %a, 6
5 6
ICE monitor command ICE monitor command
CLK
Instruction execution
A register
ICE data
judgment point ➀ ➁ ➂
The S5U1C63000H2 judges the register data at the point of "
↑
", and judges that the A register is 5 at
the point of
➁
. When the program is broken at this point, it has executed the next command of "ld %a,
6", therefore, the break is occurred after the A register is set to 6. This means that the A register content
has been changed to 6 when the content is refereed after the break. This is also applied to the break by
accessing to undefined area function.
(8) Register (data) break and hardware interrupt
The register (data) value after completion of the break operation may differ from the original setting
register (data) condition for the break. Furthermore, when a hardware interrupt is occurred in this
point, the break address shifts to the top address of the interrupt handler routine. For instance, in the
timing chart to set sequentially 5 and 6 into the A register, if the A register is 5 as a register break
condition, and a hardware interrupt is occurred while executing "ld %a, 5";
ld %a, 5 ld %a, 6
5 6
CLK
Instruction execution
A register
Interrupt factor
IACK
ICE data
judgment point
➀ ➁ ➂
In the timing chart above, if the interrupt is occurred (at the falling edge) at the point of
➀
, the
S1C63000 CPU outputs IACK to show the execution of the interruption response cycle. The interrupt
processing can not be stopped while this IACK is at low level. Therefore, the S5U1C63000H2 can not
stop the interrupt in spite of its judgment that the A register becomes 5 at the point of
➁
because the
IACK is at low level, and the break is occurred after jumping to the interrupt vector address.