14
EPSON
S5U1C63000H2 MANUAL
(S1C63 FAMILY IN-CIRCUIT EMULATOR)
CHAPTER 5: OPERATION AND FUNCTION OF S5U1C63000H2
5.6 Target Interrupt and Break
When an interrupt in the target program and a break are simultaneously occurred, the target interrupt is
prioritized. The break occurs after completing the stack operation of the interrupt. The program counter
at the break shows the top address of the interrupt handler routine. When the target program is restarted,
it executes from the top address of the interrupt handler routine.
It is the same when "I (interrupt flag) = 1" is set as the break condition by the BR command. The break
occurs when the I flag goes 1. However if an interrupt occurs simultaneously, the contents of the flags
after the break is displayed as "EICZ:0000" (the I flag is reset) because of the prioritized interrupt process.
5.7 Trace Function
In the execution of the emulation mode, information of the S1C63000 CPU (PC, instruction code, data
RAM address, data content and CPU register value) is stored into the trace memory at every CPU bus
cycle. The trace memory has a capacity of 8,192 cycles, which can store the latest instructions up to 4,096
in 2 bus cycles instruction and 2,048 in 4 bus cycles instruction.
Free space
Trace memory
Effective trace
Execution of
a program
Earliest instruction
(TP = 0)
Instruction just before
break (TP = 700)
Trace memory
Effective trace
Earliest instruction
(TP = 0)
(TP = 8,191)
Instruction just before break
Effective trace
Fig. 5.7.1 Trace function
Figure 5.7.1 shows the trace function. When the trace memory is full, old information is erased and new
information is overwritten. TP called trace pointer shows that the point of 0 means the earliest instruction
and the break point means the latest information. The maximum value of the TP is 8,191.
Latest
instruction
Trace information
Earliest
instruction
TP = 0
Trace information at any point can be displayed
by the TD command.
TP = 8,191
