Epson Endeavor Pro, Руководство пользователя

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Cache
Internal cache in the 586-class processor;
256KB, 5 12KB, or 1MB of external cache
installed on 32K x 8, 64K x 8, or 128K x 8,
3.3 volt, 15ns cache SRAM DIP chips and
two 32K x 8,28-pin, 5 volt, 15ns tag chips
(one for the tag and one for the ALT bit);
internal and external cache controllable
through SETUP
Math
Math coprocessor built into the 586-class
coprocessor
processor
Clock/
calendar
Real-time clock, calendar, and CMOS
RAM socketed on main system board with
integrated backup battery
Controlers
PCI chipset
Provides PC1 caching, memory, and
control for the PC1 bus and the
two-channel PC1 IDE interface (described
under “Hard disk and other IDE devices”
below); integrated PC1 bridge translates
CPU bus cycles to PC1 bus cycles and
CPU-to-PC1 memory write cycles to PC1
burst cycles
Video
S3
TM
Trio64
TM
PC1 VGA controller with
integrated 24-bit RAMDAC, 64-bit DRAM
interface; includes power-saving and
multimedia features; supports resolutions
up to 1280 x 1024 in 16 colors with 1MB of
video RAM, increasing to 256 colors with
2MB of video RAM; True Color support in
the 640 x 480 resolution
Specifications
A-3