emSTAMP Helium (Rev3)
18/23
The USB host interface is realized by the internal host controller of the processor. It is
compliant to the USB specification Rev. 2.0, supporting data transfers at low-speed
(1,5Mbps), full-speed (12 Mbps) and high-speed (480Mbps).
The control line USBB_PEN (PC3) from the processor module is connected to a power switch
to control the bus supply.
A logical “1”
switches the pow
er on, a logical “0” turns the power
off.
Pin
Signal
1
VBUS
2
D-
(HHSDPB)
3
D+
(HHSDMB)
4
GND
6.4
USB 2.0 Device/OTG
The USB 2.0 micro A/B port can operate in Host or Device mode. The signal USBA_ID (PC5) is
used to determine the mode of the connected device.
The interface is realized by the internal device controller of the processor. The interface is
USB 2.0 compliant, supporting data transfers at low-speed (1,5Mbps), full-speed (12 Mbps)
and high-speed (480Mbps).
If the ID signal (PC5) is tied to GND
(logical “0”)
by an external device/connector, the CPU
module enters host mode. A floating ID signal places the CPU in device mode.
In host mode bus supply can be controlled via the power switch connected to the control line
USBA_PEN (PC4). A logical “0”
swi
tches the power on, a logical “1” turns the power off.
Pin
Signal
1
VBUS
2
D-
(HHSDMA)
3
D+
(HHSDPA)
4
ID
(PC5)
5
GND
6.5
WiFi/BT
An IEEE 802.11 b/g/n link controller module with integrated Bluetooth 4.0 is placed on the
SBC. The Module is connected to FLEXCOM0 (UART mode), FLEXCOM4 (SPI mode), UART2
and some GPIOs.
emSTAMP module WiFI/BT module
PD23
SPI_SCK
PD22
SPI_MISO
