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USER MANUAL JetKit-3010 ELMA.COM
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2.4.3 Carmel CPU Complex
The CPU complex (CCPLEX) is comprised of Carmel dual-core CPU clusters in a coherent multi-
processor configuration. A high-performance System Coherency Fabric (SCF) connects all CPU
clusters enabling simultaneous operation of all CPU cores (as needed) for a true heterogeneous
multi-processing (HMP) environment. The SCF also connects CPU clusters to:
- DRAM through the Memory Controller Fabric (MCF).
- Other processing and I/O blocks in the Memory Mapped I/O (MMIO) space through an ARM
Advanced eXtensible Interface (AXI).
Each CPU cluster contains two identical Carmel processors; each core includes 128 KB Instruction
(I-cache) and 64 KB Data (D-cache) Level 1 caches, a 2 MB L2 cache is shared by both cores.
Table 3 - CPU Operation
CPU Configuration CPU Cores Max. Operating
Frequency per Core*
CPU Cluster L2 Cache L3 Cache
4x dual core 8MB 4MB 8 2.03GHz
* Refer to the documentation provided with each software release for additional information on supported power modes and
CPU operation.
Features:
- NVIDIA ® Dynamic Code Optimization
- 10-wide Superscalar architecture
- Dynamic branch prediction with a Branch Target Buffer and Global History Buffer RAMs, a return stack
buffer, and an indirect predictor.
- Full implementation of ARMv8.2 ISA compliant architecture including:
o
ARMv8 TrustZone
o
ARMv8.0 Crypto ISA
o
Trusted Memory

TZ-RAM

TZ-DRAM

Dynamic CMA VPR

GSC DRAM Carveouts

Clock Monitoring

Voltage Monitoring

Trusted Boot

Trusted Debug
o
ARMv8.2-FP16 support
- 128 KB 4-way-associative parity protected L1 instruction cache per core
- 64 KB 4-way-associative parity protected L1 data cache per core
- 2 MB 16-way-associative ECC protected L2 cache per CPU cluster
- 4 MB 16-way-associative ECC protected L3 cache (shared across all clusters)
- Performance Monitoring
- Interface to an external Generic Interrupt Controller (vGIC-400)
- Support for power management with multiple power domains