Camera Link PCI Express (PCIe) Gen1 Framegrabbers
Appendix B: Board Diagrams
EDT, Inc.
2012 March 16
28
Legacy Framegrabbers – PCIe “DV”-series
PCIe8 DV C-Link
PCIe4 DV C-Link
Base 0 /
primary
Base 1 /
secondary
Connectors
PCIe8 DV C-Link
Optional Lemo
Not to scale;
bold
= default.
PCLK FVAL
DVAL LVAL
Base 1 / secondary
Base 0 / primary
Triggering (external TTL)
1
Maximum # of lanes
(usually this jumper should be
left in the x8 position, even if the
board is in an x16, x4, or x1 slot)
FPGA boot select
Programmable
Protected
x8
x4
x1
Base 0 /
primary
Base 1 /
secondary
Connectors
PCIe8 DV C-Link
Optional Lemo
Not to scale;
bold
= default.
PCLK FVAL
DVAL LVAL
Base 1 / secondary
Base 0 / primary
Triggering (external TTL)
1
Maximum # of lanes
(usually this jumper should be
left in the x8 position, even if the
board is in an x16, x4, or x1 slot)
FPGA boot select
Programmable
Protected
x8
x4
x1
Programmable
Protected
FPGA boot select
Base 0 /
primary
Base 1 /
secondary
Connectors
PCIe4 DV C-Link
Optional Lemo
Base 1 / secondary
Base 0 / primary
Triggering (external TTL)
Not to scale;
bold
= default.
1
Programmable
Protected
FPGA boot select
Base 0 /
primary
Base 1 /
secondary
Connectors
PCIe4 DV C-Link
Optional Lemo
Base 1 / secondary
Base 0 / primary
Triggering (external TTL)
Not to scale;
bold
= default.
1