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User Manual EPT USB PLD Dev System

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UNOPROLOGIC

USB CPLD DEVELOPMENT SYSTEM

Data Sheet

The UnoProLogic is a part of the EPT USB/PLD development system. It provides an innovative
method of developing and debugging the users microcontroller code. It can also provide a high
speed data transfer mechanism between microcontroller and Host PC.

The UnoProLogic board is equipped with an Altera 5M570 PLD; which is programmed using the
Altera Quartus II software. The PLD has 570 Logic Elements which is equivalent to 440
Macrocells. An on board 66 MHz oscillator is used by the EPT-Active-Transfer-Library to
provide data transfer rates of 0.1 Mega Bytes per second. The

EPT-Active-Transfer-Library

provides control communication between the objective device and the PLD. Data transfer during
the objective device checkout between the PC and the PLD program is available via the Hyper
Serial Port. The board also includes the following parts.

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Содержание UnoProLogic

Страница 1: ...s equipped with an Altera 5M570 PLD which is programmed using the Altera Quartus II software The PLD has 570 Logic Elements which is equivalent to 440 Macrocells An on board 66 MHz oscillator is used by the EPT Active Transfer Library to provide data transfer rates of 0 1 Mega Bytes per second The EPT Active Transfer Library provides control communication between the objective device and the PLD D...

Страница 2: ...transfers and users code Four 74LVC245 bidirectional voltage translator bus transceiver 24 user Input Outputs Four Green LED s accessible by the user Two PCB switches accessible by the user All connectors to stack into the Arduino Uno USB to Serial FT2232H Dual Channel Chip 1 Block Diagram Figure 1 UNOPROLOGIC Block Diagram ...

Страница 3: ...User Manual EPT USB PLD Dev System Page 3 Figure 2 UnoProLogic Component Callouts ...

Страница 4: ...v System Page 4 2 Mechanical Dimensions 3 Pin Mapping Pin Mapping between Connectors MAXV CPLD and User code Component Pin Net Name Pin on CPLD Signal in EPT Project Pinout 66MHz Oscillator 3 GCLK 12 CLK_66MHZ Reset 2 NA 44 RST ...

Страница 5: ...3 22 JTAG_TMS Not In Project 38 BD0 19 BD_INOUT0 39 BD1 18 BD_INOUT1 40 BD2 17 BD_INOUT2 41 BD3 16 BD_INOUT3 43 BD4 15 BD_INOUT4 44 BD5 14 BD_INOUT5 45 BD6 7 BD_INOUT6 46 BD7 6 BD_INOUT7 48 BC0 5 BC_IN1 52 BC1 4 BC_IN0 53 BC2 3 BC_OUT2 54 BC3 2 BC_OUT1 55 BC4 1 BC_OUT0 SW1 1 SW_USER_1 20 SW_USER_1 SW2 1 SW_USER_2 21 SW_USER_23 U7 2 TR_DIR_1 100 TR_DIR_1 ...

Страница 6: ..._3 D1 1 LED_GR_1_N 54 LED0 D2 1 LED_GR_2_N 53 LED1 D3 1 LED_GR_3_N 52 LED2 D4 1 LED_GR_4_N 51 LED3 U9 16 ADC_EOC 67 ADC_EOC 12 ADC_CS 68 ADC_CS 13 ADC_SCLK 69 ADC_CLK 14 ADC_DIN 70 ADC_MOSI 15 ADC_DOUT 71 ADC_MISO 8 ADC_CNVST 72 ADC_CNVST U7 21 LB0 87 LB_IOH0 20 LB1 89 LB_IOH1 19 LB2 91 LB_IOH2 18 LB3 92 LB_IOH3 17 LB4 96 LB_IOH4 16 LB5 97 LB_IOH5 15 LB6 98 LB_IOH6 ...

Страница 7: ..._AD4 15 LB14 34 LB_AD5 14 LB15 33 LB_SER1 U5 21 LB16 81 LB_IOL0 20 LB17 82 LB_IOL1 19 LB18 83 LB_IOL2 18 LB19 84 LB_IOL3 17 LB20 78 LB_IOL4 16 LB21 77 LB_IOL5 15 LB22 76 LB_IOL6 14 LB23 75 LB_IOL7 4 Pushbutton switches There are two pushbutton switches on the UnoProLogic Both are momentary contact switches They include a 1uF cap to ground to debounce both switches ...

Страница 8: ...User Manual EPT USB PLD Dev System Page 8 Component Net Name Pin on CPLD Signal in EPT Project Pinout SW1 SW_USER_1 20 SW_USER_1 SW2 SW_USER_2 21 SW_USER_23 ...

Страница 9: ...de side of the LEDs are connected to an individual I O of the CPLD In order to turn on the LED the CPLD I O must apply a low signal This will complete the LED drive circuit and current will flow through the LED To turn the LED off the CPLD I O must either float or drive a high onto the pin Component Net Name Pin on CPLD Signal in EPT Project Pinout LED1 LED 1 50 LED 0 LED2 LED 2 51 LED 1 LED3 LED ...

Страница 10: ...PLD Dev System Page 10 6 Host PC Connection The UnoProLogic includes an LED that signifies the connection of the board with the Host PC The connect LED has the word CONNECT in silkscreen next to the LED This LED will only ...

Страница 11: ...er and will communicate with the UnoProLogic 7 Inputs Outputs The UnoMax is designed from the ground up as a development board for beginners All of the Inputs Outputs are protected by the 74LVC8245 transceiver chips These transceivers provide both voltage level translations and protection from over current and over voltage The transceivers can sink up to 50mA per pin There are 24 Inputs Outputs wh...

Страница 12: ...8 bits of a port will point in the same direction depending on the direction bit of the transceiver The direction bit can be changed at any time so that a port can change from input to output in minimum setup time of 6 nanoseconds Each port also has an enable pin This enable pin will enable or disable the bits of the port If the port is disabled the bits will float ...

Страница 13: ... 5 V environment and vice versa The SN74LVC4245A device is designed for asynchronous communication between data buses The device transmits data from the A bus to the B bus or from the B bus to the A bus depending on the logic level at the direction control DIR input The output enable OE input can be used to disable the device so the buses are effectively isolated The control circuitry DIR OE is po...

Страница 14: ...User Manual EPT USB PLD Dev System Page 14 7 2 Timing Characteristics 7 3 Description 24 mA drive at 3 V supply Good for heavier loads and longer traces Low VIH Allows 3 3 V to 5 V translation ...

Страница 15: ...ector The UnoMax includes a six pin analog input connector This connector provides a path from the pins to the input of the four Op Amp buffers Each Op Amp includes a 1MHz low pass filter Each Op Amp provides a buffer for the analog signals to the ADC inputs ...

Страница 16: ...Converter The EPT 5M57 AP U2 has an onboard Four Channel 10 Bit 300 KSamples second Analog to Digital Converter It has a serial SPI communications that allow the host to send setup commands and retrieve the sampled data PIN NAME FUNCTION 1 4 AIN0 AIN3 Analog Inputs ...

Страница 17: ... the interface is enabled When CS is high MOSI is high impedance 13 SCLK Serial Clock input Clocks data in and out of the serial interface 14 MISO Serial Data input MISO data is latched into the interface on the rising edge of SCLK 15 MOSI Serial Data Output Data is clocked out on the falling edge of SCLK High impedance when CS is connected to VDD 16 EOC End of Conversion Output Data is valide aft...

Страница 18: ...e The MAX11618 MAX11621 MAX11624 MAX11625 feature a serial interface compatible with SPI QSPI and MICROWIRE devices For SPI QSPI ensure the CPU serial interface runs in master mode so it generates the serial clock signal Select the SCLK frequency of 10MHz or less and set clock polarity CPOL and phase ...

Страница 19: ...ST to request conversions one channel at a time controlling the sampling speed without tying up the serial bus Request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10 Use clock mode 11 with SCLK up to 4 8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps Clock mode 11 disables scanning...

Страница 20: ...User Manual EPT USB PLD Dev System Page 20 ...

Страница 21: ...X11618 communicate between the internal registers and the external circuitry through the SPI QSPI compatible serial interface Table 1 details the registers and the bit names Tables 2 5 show the various functions within the conversion register setup register averaging register ...

Страница 22: ...r when in clock mode 10 or 11 or by applying a low pulse to the CNVST pin when in clock mode 00 or 01 A conversion is not performed if it is requested on a channel that has been configured as CNVST Select scan mode 00 or 01 to return one result per single ended channel within the requested range Select scan mode 10 to scan a single input channel numerous times depending on NSCAN1 and NSCAN0 in the...

Страница 23: ...register to configure the clock reference and power down modes Table 3 details the bits in the setup register Bits 5 and 4 CKSEL1 and CKSEL0 control the clock mode acquisition and sampling and the conversion start Bits 3 and 2 REFSEL1 and REFSEL0 control internal or external reference use ...

Страница 24: ...d result and to independently control the number of results requested for single channel scans Table 2 details the four scan modes available in the conversion register All four scan modes allow averaging as long as the AVGON bit bit 4 in the averaging register is set to 1 Select scan mode 10 to scan the same channel multiple times Clock mode 11 disables averaging ...

Страница 25: ...eset Register Write to the reset register as shown in Table 5 to clear the FIFO or to reset all registers to their default states Set the RESET bit to 1 to reset the FIFO Set the reset bit to zero to return the MAX11618 to the default power up state ...

Страница 26: ...s and the FT2232H has built in JTAG signals 11 Oscillator There is a 66MHz oscillator on the UnoProLogic This oscillator has the following Vendor and P N 1 66MHz Renesas Electronics America Inc P N XLH536066 000000I This oscillators are connected to the Global Clock inputs on the FPGA Both devices provide stable clock for the FPGA s internal DLL s The user can access these clock sources by calling...

Страница 27: ...stem Page 27 the net connected to the FPGA pin Component Net Name Pin on CPLD Signal in EPT Project Pinout 66MHz Osc GCLK1 23 CLK_66MHZ XLH536066 000000I PARAMETERS MAX unless otherwise noted Frequency 66MHz Supply Voltage VDD 3 3V ...

Страница 28: ...aces The two channels can also be independently configured to use an MPSSE engine This allows the two ports of the FT2232HQ to operate independently as UART Bit Bang ports or MPSSE engines used to emulate JTAG SPI I2C Bit bang or other synchronous serial modes The chip is powered by 3 3V and includes an internal 1 8V regulator to power the chip core It uses 3 3V I O interfacing and is 5V Tolerant ...

Страница 29: ... The USB supplies a maximum of 5V 500mA s The components of the UnoProLogic must share this power with the user code that will run inside the FPGA along with any external power use 13 1 Core Board Power Budget Device Part Number 1 8V Power 3 3V Power CPLD 5M570 Defined by user code EPT Transfer Demo code 50mA Defined by user code EPT Transfer Demo code 50mA ...

Страница 30: ...USB EEPROM 93LC56 2 mA write current 1 mA read current 66MHz Oscillator CB3LV 3I 66M0 10 mA ADC Four Channel MAX11618EEE 17 mA Op Amp driver MCP6L04 0 5 mA all four amps active Schmitt Buffer 74LVC1G17SE 1mA User LEDs 20 mA Total 50mA 175 5mA Theoritical Values only This data needs to be validated 13 2 Core Board VUSB Power Budget Device Part Number VUSB ...

Страница 31: ...User Manual EPT USB PLD Dev System Page 31 1 8V Power Supply MCP1725 1802E 70mA 3 3V Power Supply MCP1725 3302E 215mA Total 285mA Theoritical Values only This data needs to be validated ...

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