® 16k CXP
20
UM 16k CXP – Indice E - 06/13
e2v semiconductors SAS 2013
6.2.2
Image Format
Feature
Description
SensorWidth
Get sensor physical width : 16384
SensorHeight
1
WidthMax
Mapped on SensorWidth : 16384 or 8192 in binning mode
HeightMax
1
Width
Mapped on SensorWidth : 16384 or 8192 in binning mode
Height
1
InputSource
Signal source from CMOS sensor, processing chain activated
SensorMode
1S
: Set sensor mode to DualLine “1S” (outputted line = B).
2S
: sensor mode to MultiLine “2S” (outputted line = B+C).,
4S
: Set sensor mode to QuadriLine “4S” (outputted line = (A+B)+(C+D)).
1SB
: Set sensor mode to MonoLine “1SB” (1S with binning A+B)),
2SB
: Set sensor mode to DualLine “2SB” (2S with binning (A+B)+(C+D)),
MultiLineGain
x1
: Set MultiLine gain to “x1”
x1/2
: Set MultiLine gain to “x1/2” (not available if SensorMode = 0 (“1S” mode)
ReverseX
Reverse the output reading direction of the sensor
0ff
: Set reverse reading to “disable”
On
: Set reverse reading to “enable”
PixelFormat
0x0101
: Mono8
0x0102
: Mono10
0x0103
: Mono12
PixelCoding
Mono
PixelSize
Bpp8, Bpp10 or Bpp12 depending on PixelFormat
PixelColorFilter
None
PixelDynamicRangeMin
0
PixelDynamicRangeMin
255, 1023 or 4095 depending on PixelFormat
TestImageSelector
0ff
: Image pattern disabled
Grey Horizontal Ramp
: Set image pattern to a Grey Horizontal Ramp,
White
: Set image pattern to a full White pattern.
Gray Pattern
: Set image pattern to a gray pattern (Half Dynamic)
Black
: Set image pattern to a full Black pattern,
GreyVerticalRampMoving
: Set image pattern to Grey Vertical Ramp Moving
6.2.2.1
Structure of the Sensor
In 2S Mode, the summation of the two
lines is done in the FPGA :
B+C
In 4S Mode, the summation of the two
double lines is done in the FPGA :
(AB )+ (BC)
ADC
ADC
Memory node
Pixel Line A
Pixel Line B
Pixel Line C
Pixel Line D
Memory node
Web Direction
2S
1S
4S
Exposure
delays
FPGA