
15
Note(s):
(1) Only one field (or half the normal vertical resolution) per integration period is obtained.
(2) Since charge transfer is initiated only when the RESET pulse is asserted (LOW), there is no
image generated by the camera except the one field due to each INTEGRATION
sequence.Therefore the monitor screen remains blank, until the next INTEGRATION sequence
is initiated by the next falling edge of RESET.
(3) The Pulse Driven Integration mode is designed for applications where the user has complete
control of the integration period. When the Pulse Driven Integration mode is selected (using the
Mode Control bits), the CCD does NOT integrate charge until the RESET pulse is asserted LOW.
Therefore, as long as RESET is HIGH, the camera does NOT produce an image. However, clock
and sync. are generated, so that a frame grabber (or image processor) can be in synchronization
with the camera. The Enable Frame and Enable Line signals are also generated. Since the
camera does not produce an image while it is waiting for an active LOW RESET pulse, any
frames of video data that are captured (or viewed on a monitor) during this waiting period will be
black.
(4) When the RESET pulse transitions (HIGH to LOW) the CCD is flushed (cleared of charge) by
means of two quick, successive charge transfers. As soon as the CCD is flushed, the active
integration period begins. This period lasts as long as the RESET pulse is LOW. During this
period, the Enable Frame and Enable Line signals are NOT asserted, since no active video is
being generated while the integration takes place.
(5) When the RESET pulse transitions (LOW to HIGH) the final “readout” transfer takes place.
The timing chip is also reset to line 6 of the ODD field (simultaneous to the readout transfer in
the CCD). Active video is output starting at line 20 (standard RS-170 format). The Enable Frame
and Enable Line signals are generated, beginning at line 20. This is the image of the scene that
was integrated on the CCD during the LOW duration of the RESET pulse.
(6) There is no lower or upper theoretical limit to the integration period. In reality, the upper limit
is determined by the amount of noise that can be tolerated and the dynamic range required by
the application. The lower limit is determined by the amount of light during image transfer and
the amount of smear that can be tolerated by the application. Cooling the CCD will result in
longer usable integration periods due to a reduction in the dark current of the CCD.
5.4 N FIELD INTEGRATION:
If the N Field Integration mode is selected, the following sequence is followed.
Figure 5-4: "N" Field Integration Mode
The CCD is flushed by means of two quick, successive transfers. This takes approximately
140
µ
sec. At the end of this period, the Integration Period begins.
Содержание DigitEyes Series
Страница 14: ...9 Figure 4 3 TC 245 Gate Level Drawing Texas Instruments 1994 ...
Страница 61: ...56 12 Appendix D Camera Mechanical Drawings Figure 12 1 Camera Mechanical Drawings ...
Страница 63: ...58 Figure 13 2 Camera Noise Spectrum Min Gain Bandwidth 10kHz to 4 2MHz ...
Страница 64: ...59 Figure 13 3 Camera Noise Spectrum Max Gain Bandwidth 100kHz to 4 2Mhz ...
Страница 65: ...60 Figure 13 4 Camera Noise Spectrum Max Gain Bandwidth 10kHz to full ...