Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
Bits 31-16: “Configuration Register” address in (only addresses 0xDF00-0xDFFF are valid. See
the “Configuration Register” map in the “Configuration Section” section)
Bits 15-8: Ignored
Bits 7-0: The Data value to write to the register
Reads
To read from a configuration register, read one byte from PCI at the following 32-bit address:
Bits 31-24: The DN9002K10PCI’s BAR0
Bits 23-16: the lower 8 bits of the address of the configuration register you would like to read.
(The upper 8 bits must be 0xDF, or the read will not be valid).
Bits 15-0: 0x0260
Example
Example: Set clock G0 to 250Mhz
Step 1) Determine the M and N values required for the G0 PLL. See the clocking section to
details on the G0 clock synthesis. (The correct values are M=20 and N=2)
Step 2) Look on the “Configuration Registers” memory map in the Configuration Section and find
the entries for G0 M (multiply) and G0 N (divide) values.
Step 3) Write to the G0 M register the value 0x14 (20). Write to BAR0, offset 0x258:
0xDF300014
Step 4) Write to the G0 N register the value 0x01 (2). Write to BAR0, offset 0x258:
0xDF290001
Step 5) Write to the UPDATE_FLAG register the value 0x01 (CLK G0). Write to BAR0, offset
0x258:
0xDF400001
7.2.3 Main Bus
The Main Bus interface is how you can communicate to all FPGAs on the DN9002K10PCI
over PCI (not just FPGA A). The bandwidth available over the Main Bus is much lower than
that of PCI, so performance is not as great using this method. For details about the Main Bus,
see the Main Bus section in this chapter.
To write to Main Bus over PCI, write to BAR0 at the address QLPCI_REG_MBADDR with
the 32-bit value representing the main bus address you would like to write to. Then, write a
second PCI write to address QLPCI_REG_MBWRDATA with 32-bit data representing the
DN9002K10PCI User Guide www.dinigroup.com 84