Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
Access to PCI is split between the configuration circuit and FPGA A. Access to the
configuration functions of the DN9002K10PCI (FPGA configuration, clocks, etc.) are
controlled by the configuration circuit and do not use FPGA A at all.
The user design in FPGA A can access BAR 2,3,4,5 and two DMA channels. Bar 0 and 1 are
reserved by the QL5064 control functions and by the configuration circuitry of the
DN9002K10PCI. Since there is a PCI device controller in the QL5064, the PCI protocol
controller does not need to take any of the user space in the FPGA, however, the Dini Group
provides an interface module that should be used in FPGA A. This module takes care of IO and
clocking concerns, and arbitration of some signals on the QL5064 that are shared with the
configuration circuitry.
7.1 FPGA Interface
The FPGA is required to use the supplied “QL5064_Interface_module” provided on the user
CD. This module provides an east FIFO interface for target accesses and DMA. This interface
is described briefly here, but you should see the document on the user CD:
D:\FPGA_Reference_Designs\DN9002K10PCI\PCI_interface\
QL5064_Interface_Module.pdf
DN9002K10PCI User Guide www.dinigroup.com 80