PCM5100PWR (DIGITAL_NETWORK : IC765)
Block diagram
PCM5100, PCM5101, PCM5102
SLAS764
–
MAY 2011
www.ti.com
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510x
PCM510X (top view)
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CPVDD
1
-
Charge pump power supply, 3.3V
CAPP
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
-
Charge pump ground
CAPM
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
O
Negative charge pump rail terminal for decoupling, -3.3V
OUTL
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
AVDD
8
-
Analog power supply, 3.3V
AGND
9
-
Analog ground
DEMP
10
I
De-emphasis control for 44.1kHz sampling rate
(1)
: Off (Low) / On (High)
FLT
11
I
Filter select : Normal latency (Low) / Low latency (High)
SCK
12
I
System clock input
BCK
13
I
Audio data bit clock input
DIN
14
I
Audio data input
LRCK
15
I
Audio data word clock input
FMT
16
I
Audio format selection : I
2
S (Low) / Left justified (High)
XSMT
17
I
Soft mute control : Soft mute (Low) / soft un-mute (High)
LDOO
18
-
Internal logic supply rail terminal for decoupling
DGND
19
-
Digital ground
DVDD
20
-
Digital power supply, 3.3V
(1) Failsafe LVCMOS Schmitt trigger input
6
Copyright
©
2011, Texas Instruments Incorporated
A
udi
o
Int
er
fac
e
8x
Int
er
pol
at
ion
F
ilt
er
32b
it
∆
Σ
M
od
ul
at
or
Current
Segment
DAC
Current
Segment
DAC
I/V
I/V
A
na
lo
g
M
ut
e
A
na
lo
g
M
ut
e
Zero
Data
Detector
UVP/Reset
PLL Clock
Power
Supply
Ch. Pump
POR
Clock Halt
Detection
Advanced Mute Control
MCK
BCK
LRCK
C
A
P
P
C
A
P
M
V
N
E
G
LINE OUT
DIN (i2s)
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
DVDD (3.3V)
GND
PCM5100, PCM5101, PCM5102
SLAS764
–
MAY 2011
www.ti.com
Table 1. Differences Between PCM510x Devices
Part Number
Dynamic Range
SNR
THD
PCM5102
112dB
112dB
–
93dB
PCM5101
106dB
106dB
–
92dB
PCM5100
100dB
100dB
–
90dB
spacer
Figure 1. PCM510x Functional Block Diagram
2
Copyright
©
2011, Texas Instruments Incorporated
AD8195 (F-HDMI : IC811)
AD8195 Terminal Functions
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1
IN0
2
IP0
3
IN1
4
IP1
5
VTTI
6
IN2
7
IP2
10
AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40
SC
L_
IN
39
SD
A_
IN
38
CE
C_
IN
37
A
VE
E
36
VR
EF
_I
N
35
SC
L_
O
UT
34
SD
A_
O
UT
31
CE
C_
O
UT
11
O
N0
12
O
P0
13
VT
TO
14
O
N1
15
O
P1
16
AV
CC
17
O
N2
20
O
P3
9
IP3
8
IN3
22 AVCC
23 AVCC
19
O
N3
18
O
P2
32
AMU
XV
CC
33
VR
EF
_O
UT
PIN 1
INDICATOR
Mnemonic
IN0
IP0
IN1
IP1
VTTI
IN2
IP2
IN3
IP3
AVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
COMP
AVEE
TX_EN
PE_EN
CEC_OUT
AMUXVCC
VREF_OUT
SDA_OUT
SCL_OUT
VREF_IN
CEC_IN
SDA_IN
SCL_IN
Type
1
HS I
HS I
HS I
HS I
Power
HS I
HS I
HS I
HS I
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Power
Control
Control
LS I/O
Power
Reference
LS I/O
LS I/O
Reference
LS I/O
LS I/O
LS I/O
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Preemphasis Enable Parallel Interface.
CEC Output Side.
Positive Auxiliary Buffer Supply. 5 V nominal.
DDC Output Side Pull-Up Reference Voltage.
DDC Output Side Data Line Input/Output.
DDC Output Side Clock Line Input/Output.
DDC Input Side Pull-Up Reference Voltage.
CEC Input Side.
DDC Input Side Data Line.
DDC Input Side Clock Line
Pin No.
1
2
3
4
5
6
7
8
9
10, 16, 22, 23, 25, 26, 30
11
12
13
14
15
17
18
19
20
21
24, 27, 37, Exposed Pad
28
29
31
32
33
34
35
36
38
39
40
1
HS = high speed, LS = low speed, I = input, and O = output.
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1
IN0
2
IP0
3
IN1
4
IP1
5
VTTI
6
IN2
7
IP2
10
AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40
SC
L_
IN
39
SD
A_
IN
38
CE
C_
IN
37
A
VE
E
36
VR
EF
_I
N
35
SC
L_
O
UT
34
SD
A_
O
UT
31
CE
C_
O
UT
11
O
N0
12
O
P0
13
VT
TO
14
O
N1
15
O
P1
16
AV
CC
17
O
N2
20
O
P3
9
IP3
8
IN3
22 AVCC
23 AVCC
19
O
N3
18
O
P2
32
AMU
XV
CC
33
VR
EF
_O
UT
PIN 1
INDICATOR
Mnemonic
IN0
IP0
IN1
IP1
VTTI
IN2
IP2
IN3
IP3
AVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
COMP
AVEE
TX_EN
PE_EN
CEC_OUT
AMUXVCC
VREF_OUT
SDA_OUT
SCL_OUT
VREF_IN
CEC_IN
SDA_IN
SCL_IN
Type
1
HS I
HS I
HS I
HS I
Power
HS I
HS I
HS I
HS I
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Power
Control
Control
LS I/O
Power
Reference
LS I/O
LS I/O
Reference
LS I/O
LS I/O
LS I/O
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Preemphasis Enable Parallel Interface.
CEC Output Side.
Positive Auxiliary Buffer Supply. 5 V nominal.
DDC Output Side Pull-Up Reference Voltage.
DDC Output Side Data Line Input/Output.
DDC Output Side Clock Line Input/Output.
DDC Input Side Pull-Up Reference Voltage.
CEC Input Side.
DDC Input Side Data Line.
DDC Input Side Clock Line
Pin No.
1
2
3
4
5
6
7
8
9
10, 16, 22, 23, 25, 26, 30
11
12
13
14
15
17
18
19
20
21
24, 27, 37, Exposed Pad
28
29
31
32
33
34
35
36
38
39
40
1
HS = high speed, LS = low speed, I = input, and O = output.
54
Caution in
servicing
Electrical
Mechanical
Repair Information
Updating
Содержание AVR-S730H
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